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authorRichard Trieu <rtrieu@google.com>2018-01-26 21:55:13 +0000
committerRichard Trieu <rtrieu@google.com>2018-01-26 21:55:13 +0000
commit8610c9f43a386ee40cbfd7addb507434205b2cc4 (patch)
tree029034165ffc9ccdf28a527f5af58950c70bcf26 /llvm/lib
parent90ca4e8b0c2785b03f5a7c29277bab6fd77fc195 (diff)
downloadbcm5719-llvm-8610c9f43a386ee40cbfd7addb507434205b2cc4.tar.gz
bcm5719-llvm-8610c9f43a386ee40cbfd7addb507434205b2cc4.zip
Inline variable only used within assert.
llvm-svn: 323569
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonVExtract.cpp3
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonVExtract.cpp b/llvm/lib/Target/Hexagon/HexagonVExtract.cpp
index 67c201d1916..929ac2bd0d9 100644
--- a/llvm/lib/Target/Hexagon/HexagonVExtract.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVExtract.cpp
@@ -140,9 +140,8 @@ bool HexagonVExtract::runOnMachineFunction(MachineFunction &MF) {
for (MachineInstr *ExtI : P.second) {
assert(ExtI->getOpcode() == Hexagon::V6_extractw);
- unsigned VR = ExtI->getOperand(1).getReg();
unsigned SR = ExtI->getOperand(1).getSubReg();
- assert(VR == VecR);
+ assert(ExtI->getOperand(1).getReg() == VecR);
MachineBasicBlock &ExtB = *ExtI->getParent();
DebugLoc DL = ExtI->getDebugLoc();
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