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| author | Craig Topper <craig.topper@intel.com> | 2018-01-27 23:49:14 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-01-27 23:49:14 +0000 |
| commit | 5e4b45361f5da80f42a502e120bd3352a0f3d68a (patch) | |
| tree | 7db3e912fba49b0f15b4ea0d95c42a2c5a4f455b /llvm/lib | |
| parent | 540daee124df778764e7a610d3b38fac85e12efb (diff) | |
| download | bcm5719-llvm-5e4b45361f5da80f42a502e120bd3352a0f3d68a.tar.gz bcm5719-llvm-5e4b45361f5da80f42a502e120bd3352a0f3d68a.zip | |
[X86] Add patterns for using masked vptestnmd for 256-bit vectors without VLX.
We can widen the mask and extract it back down.
llvm-svn: 323610
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 37 |
1 files changed, 24 insertions, 13 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index b4e68f20c11..e095011d875 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -2958,19 +2958,19 @@ defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86kshiftr, SSE_PSHU multiclass axv512_icmp_packed_no_vlx_lowering<PatFrag Frag, string InstStr, X86VectorVTInfo Narrow, X86VectorVTInfo Wide> { -def : Pat<(Narrow.KVT (Frag (Narrow.VT Narrow.RC:$src1), + def : Pat<(Narrow.KVT (Frag (Narrow.VT Narrow.RC:$src1), (Narrow.VT Narrow.RC:$src2))), (COPY_TO_REGCLASS - (!cast<Instruction>(InstStr##Zrr) + (!cast<Instruction>(InstStr#"Zrr") (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)), (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx))), Narrow.KRC)>; -def : Pat<(Narrow.KVT (and Narrow.KRC:$mask, - (Frag (Narrow.VT Narrow.RC:$src1), + def : Pat<(Narrow.KVT (and Narrow.KRC:$mask, + (Frag (Narrow.VT Narrow.RC:$src1), (Narrow.VT Narrow.RC:$src2)))), (COPY_TO_REGCLASS - (!cast<Instruction>(InstStr##Zrrk) + (!cast<Instruction>(InstStr#"Zrrk") (COPY_TO_REGCLASS Narrow.KRC:$mask, Wide.KRC), (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)), (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx))), @@ -5232,14 +5232,25 @@ multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode, // Use 512bit version to implement 128/256 bit in case NoVLX. multiclass avx512_vptest_lowering<SDNode OpNode, X86VectorVTInfo ExtendInfo, X86VectorVTInfo _, string Suffix> { - def : Pat<(_.KVT (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))), - (_.KVT (COPY_TO_REGCLASS - (!cast<Instruction>(NAME # Suffix # "Zrr") - (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), - _.RC:$src1, _.SubRegIdx), - (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), - _.RC:$src2, _.SubRegIdx)), - _.KRC))>; + def : Pat<(_.KVT (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))), + (_.KVT (COPY_TO_REGCLASS + (!cast<Instruction>(NAME # Suffix # "Zrr") + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src1, _.SubRegIdx), + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src2, _.SubRegIdx)), + _.KRC))>; + + def : Pat<(_.KVT (and _.KRC:$mask, + (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))), + (COPY_TO_REGCLASS + (!cast<Instruction>(NAME # Suffix # "Zrrk") + (COPY_TO_REGCLASS _.KRC:$mask, ExtendInfo.KRC), + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src1, _.SubRegIdx), + (INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)), + _.RC:$src2, _.SubRegIdx)), + _.KRC)>; } multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode, |
