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* R600: Remove predicated_break instVincent Lejeune2013-07-314-59/+7
| | | | | | | | | | | | | We were using two instructions for similar purpose : break and predicated break. Only predicated_break was emitted and it was lowered at R600ControlFlowFinalizer to JUMP;CF_BREAK;POP. This commit simplify the situation by making AMDILCFGStructurizer emit IF_PREDICATE;BREAK;ENDIF; instead of predicated_break (which is now removed). There is no functionality change. llvm-svn: 187510
* Reject bitcasts between address spaces with different sizesMatt Arsenault2013-07-311-20/+104
| | | | llvm-svn: 187506
* [SystemZ] Implement isLegalAddressingMode()Richard Sandiford2013-07-312-3/+21
| | | | | | | | | | The loop optimizers were assuming that scales > 1 were OK. I think this is actually a bug in TargetLoweringBase::isLegalAddressingMode(), since it seems to be trying to reject anything that isn't r+i or r+r, but it has no default case for scales other than 0, 1 or 2. Implementing the hook for z means that z can no longer test any change there though. llvm-svn: 187497
* [SystemZ] Be more careful about inverting CC masks (conditional loads)Richard Sandiford2013-07-315-31/+31
| | | | | | | | Extend r187495 to conditional loads. I split this out because the easiest way seemed to be to force a particular operand order in SystemZISelDAGToDAG.cpp. llvm-svn: 187496
* [SystemZ] Be more careful about inverting CC masksRichard Sandiford2013-07-319-81/+137
| | | | | | | | | | | | | | | | | | | | | | | | System z branches have a mask to select which of the 4 CC values should cause the branch to be taken. We can invert a branch by inverting the mask. However, not all instructions can produce all 4 CC values, so inverting the branch like this can lead to some oddities. For example, integer comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater). If an integer EQ is reversed to NE before instruction selection, the branch will test for 1 or 2. If instead the branch is reversed after instruction selection (by inverting the mask), it will test for 1, 2 or 3. Both are correct, but the second isn't really canonical. This patch therefore keeps track of which CC values are possible and uses this when inverting a mask. Although this is mostly cosmestic, it fixes undefined behavior for the CIJNLH in branch-08.ll. Another fix would have been to mask out bit 0 when generating the fused compare and branch, but the point of this patch is that we shouldn't need to do that in the first place. The patch also makes it easier to reuse CC results from other instructions. llvm-svn: 187495
* [SystemZ] Move compare-and-branch generation even laterRichard Sandiford2013-07-314-136/+119
| | | | | | | | | | | | | | | | | | | | | | | r187116 moved compare-and-branch generation from the instruction-selection pass to the peephole optimizer (via optimizeCompare). It turns out that even this is a bit too early. Fused compare-and-branch instructions don't interact well with predication, where a CC result is needed. They also make it harder to reuse the CC side-effects of earlier instructions (not yet implemented, but the subject of a later patch). Another problem was that the AnalyzeBranch family of routines weren't handling compares and branches, so we weren't able to reverse the fused form in cases where we would reverse a separate branch. This could have been fixed by extending AnalyzeBranch, but given the other problems, I've instead moved the fusing to the long-branch pass, which is also responsible for the opposite transformation: splitting out-of-range compares and branches into separate compares and long branches. I've added a test for the AnalyzeBranch problem. A test for the predication problem is included in the next patch, which fixes a bug in the choice of CC mask. llvm-svn: 187494
* Fixed assertion in Extract128BitVector()Elena Demikhovsky2013-07-311-1/+2
| | | | llvm-svn: 187493
* [SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()Richard Sandiford2013-07-314-79/+193
| | | | | | | | | | | | | | | | | | | | | | r186399 aggressively used the RISBG instruction for immediate ANDs, both because it can handle some values that AND IMMEDIATE can't, and because it allows the destination register to be different from the source. I realized later while implementing the distinct-ops support that it would be better to leave the choice up to convertToThreeAddress() instead. The AND IMMEDIATE form is shorter and is less likely to be cracked. This is a problem for 32-bit ANDs because we assume that all 32-bit operations will leave the high word untouched, whereas RISBG used in this way will either clear the high word or copy it from the source register. The patch uses the z196 instruction RISBLG for this instead. This means that z10 will be restricted to NILL, NILH and NILF for 32-bit ANDs, but I think that should be OK for now. Although we're using z10 as the base architecture, the optimization work is going to be focused more on z196 and zEC12. llvm-svn: 187492
* Added INSERT and EXTRACT intructions from AVX-512 ISA.Elena Demikhovsky2013-07-316-181/+811
| | | | | | | | | All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms. Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors. Added lowering for EXTRACT/INSERT subvector for 512-bit vectors. Added a test. llvm-svn: 187491
* [SystemZ] Add RISBLG and RISBHG instruction definitionsRichard Sandiford2013-07-314-3/+19
| | | | | | The next patch will make use of RISBLG for codegen. llvm-svn: 187490
* Add parentheses to silence gcc warning.Richard Trieu2013-07-311-4/+4
| | | | llvm-svn: 187482
* Increment arg_count inside the loop in printInline. Patch by Joe Matarazzo.Craig Topper2013-07-311-1/+1
| | | | llvm-svn: 187477
* Changed register names (and pointer keywords) to be lower case when using ↵Craig Topper2013-07-319-230/+225
| | | | | | | | Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
* Fix a severe compile time problem when forming large SCEV expressions.Andrew Trick2013-07-311-0/+3
| | | | | | | | | | | | This fix is very lightweight. The same fix already existed for AddRec but was missing for NAry expressions. This is obviously an improvement and I'm unsure how to test compile time problems. Patch by Xiaoyi Guo! llvm-svn: 187475
* Remove trailing whitespace and some tab characters.Craig Topper2013-07-311-9/+9
| | | | llvm-svn: 187472
* Fixed incorrect disassembly for MOV16o16a when using Intel syntax.Craig Topper2013-07-311-2/+2
| | | | | | Patch by Richard Mitton. llvm-svn: 187471
* Fix crashing on invalid inline asm with matching constraints.Eric Christopher2013-07-311-15/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For a testcase like the following: typedef unsigned long uint64_t; typedef struct { uint64_t lo; uint64_t hi; } blob128_t; void add_128_to_128(const blob128_t *in, blob128_t *res) { asm ("PAND %1, %0" : "+Q"(*res) : "Q"(*in)); } where we'll fail to allocate the register for the output constraint, our matching input constraint will not find a register to match, and could try to search past the end of the current operands array. On the idea that we'd like to attempt to keep compilation going to find more errors in the module, change the error cases when we're visiting inline asm IR to return immediately and avoid trying to create a node in the DAG. This leaves us with only a single error message per inline asm instruction, but allows us to safely keep going in the general case. llvm-svn: 187470
* [mips] Rename instruction DANDi to ANDi64.Akira Hatanaka2013-07-311-4/+4
| | | | | | No functionality change. llvm-svn: 187469
* [mips] Define instruction itineraries IIArith and IILogic.Akira Hatanaka2013-07-315-38/+49
| | | | | | No functionality change. llvm-svn: 187468
* Fix ptr vector inconsistency in CreatePointerCastMatt Arsenault2013-07-311-5/+13
| | | | | | | | One form would accept a vector of pointers, and the other did not. Make both accept vectors of pointers, and add an assertion for the number of elements. llvm-svn: 187464
* Fix windows' implementation of status when a file doesn't exist.Rafael Espindola2013-07-311-6/+11
| | | | | | | | | The unix one was returning no_such_file_or_directory, but the windows one was return success. Update the one one caller that was depending on the old behavior. llvm-svn: 187463
* Preserve fast-math flags when folding (fsub x, (fneg y)) to (fadd x, y).Owen Anderson2013-07-301-4/+11
| | | | llvm-svn: 187462
* Reflow this to be easier to read.Eric Christopher2013-07-301-7/+5
| | | | llvm-svn: 187459
* Respect address space sizes in isEliminableCastPair.Matt Arsenault2013-07-302-14/+52
| | | | | | | This avoids constant folding bitcast/ptrtoint/inttoptr combinations that have illegal bitcasts between differently sized address spaces. llvm-svn: 187455
* Revert "Remove isCastable since nothing uses it now"Matt Arsenault2013-07-301-0/+63
| | | | | | Apparently dragonegg uses it. llvm-svn: 187454
* Remove isCastable since nothing uses it nowMatt Arsenault2013-07-301-63/+0
| | | | llvm-svn: 187448
* isKnownToBeAPowerOfTwo: Strengthen isKnownToBeAPowerOfTwo's analysis on add ↵David Majnemer2013-07-301-16/+30
| | | | | | | | | instructions Call into ComputeMaskedBits to figure out which bits are set on both add operands and determine if the value is a power-of-two-or-zero or not. llvm-svn: 187445
* Change behavior of calling bitcasted alias functions.Matt Arsenault2013-07-302-11/+53
| | | | | | | | It will now only convert the arguments / return value and call the underlying function if the types are able to be bitcasted. This avoids using fp<->int conversions that would occur before. llvm-svn: 187444
* [mips] Delete instruction format for "bal".Akira Hatanaka2013-07-301-11/+0
| | | | llvm-svn: 187443
* Implement getUniqueID for directories on windows.Rafael Espindola2013-07-301-18/+14
| | | | llvm-svn: 187441
* [mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias thatAkira Hatanaka2013-07-302-5/+9
| | | | | | turns "bal" into "bgezal". llvm-svn: 187440
* Remove dead code.Rafael Espindola2013-07-301-3/+0
| | | | llvm-svn: 187439
* Down-scale slot index distance to save bits.Andrew Trick2013-07-301-1/+1
| | | | llvm-svn: 187438
* MI Sched: Track live-thru registers.Andrew Trick2013-07-302-12/+67
| | | | | | | | | | | When registers must be live throughout the scheduling region, increase the limit for the register class. Once we exceed the original limit, they will be spilled, and there's no point further reducing pressure. This isn't a perfect heuristics but avoids a situation where the scheduler could become trapped by trying to achieve the impossible. llvm-svn: 187436
* MI Sched fix: assert "Disconnected LRG within the scheduling region."Andrew Trick2013-07-301-0/+6
| | | | llvm-svn: 187435
* [Sparc] Rewrite MBB's live-in registers for leaf functions. Also, addVenkatraman Govindaraju2013-07-302-7/+20
| | | | | | | | register i7 as a live-in if current function's return address is taken. This revision fixes PR16269. llvm-svn: 187433
* Implement TokenizeWindowsCommandLine.Rui Ueyama2013-07-301-1/+101
| | | | | | | | | | This is a follow up patch for r187390 to implement the parser for the Windows-style command line. This should follow the rule as described at http://msdn.microsoft.com/en-us/library/windows/desktop/17w5ykft(v=vs.85).aspx Differential Revision: http://llvm-reviews.chandlerc.com/D1235 llvm-svn: 187430
* R600/SI: Expand vector fp <-> int conversionsTom Stellard2013-07-302-4/+4
| | | | llvm-svn: 187421
* This patch implements parsing of mips FCC register operands. The example ↵Vladimir Medic2013-07-304-14/+66
| | | | | | instructions have been added to test files. llvm-svn: 187410
* [ARM] check bitwidth in PerformORCombineSaleem Abdulrasool2013-07-301-14/+21
| | | | | | | | | | | | | When simplifying a (or (and B A) (and C ~A)) to a (VBSL A B C) ensure that the bitwidth of the second operands to both ands match before comparing the negation of the values. Split the check of the value of the second operands to the ands. Move the cast and variable declaration slightly higher to make it slightly easier to follow. Bug-Id: 16700 Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org> llvm-svn: 187404
* [Sparc] Use call's debugloc for the unimp instruction.Venkatraman Govindaraju2013-07-301-1/+1
| | | | llvm-svn: 187402
* [PowerPC] Skeletal FastISel support for 64-bit PowerPC ELF.Bill Schmidt2013-07-305-1/+347
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the first of many upcoming patches for PowerPC fast instruction selection support. This patch implements the minimum necessary for a functional (but extremely limited) FastISel pass. It allows the table-generated portions of the selector to be created and used, but in most cases selection will fall back to the DAG selector. None of the block terminator instructions are implemented yet, and most interesting instructions require some special handling. Therefore there aren't any new test cases with this patch. There will be quite a few tests coming with future patches. This patch adds the make/CMake support for the new code (including tablegen -gen-fast-isel) and creates the FastISel object for PPC64 ELF only. It instantiates the necessary virtual functions (TargetSelectInstruction, TargetMaterializeConstant, TargetMaterializeAlloca, tryToFoldLoadIntoMI, and FastLowerArguments), but of these, only TargetMaterializeConstant contains any useful implementation. This is present since the table-generated code requires the ability to materialize integer constants for some instructions. This patch has been tested by building and running the projects/test-suite code with -O0. All tests passed with the exception of a couple of long-running tests that time out using -O0 code generation. llvm-svn: 187399
* [R600] Replicate old DAGCombiner behavior in target specific DAG combine.Quentin Colombet2013-07-301-0/+56
| | | | | | | build_vector is lowered to REG_SEQUENCE, which is something the register allocator does a good job at optimizing. llvm-svn: 187397
* [DAGCombiner] insert_vector_elt: Avoid building a vector twice.Quentin Colombet2013-07-301-1/+3
| | | | | | | | | | | | | | | | This patch prevents the following combine when the input vector is used more than once. insert_vector_elt (build_vector elt0, ..., eltN), NewEltIdx, idx => build_vector elt0, ..., NewEltIdx, ..., eltN The reasons are: - Building a vector may be expensive, so try to reuse the existing part of a vector instead of creating a new one (think big vectors). - elt0 to eltN now have two users instead of one. This may prevent some other optimizations. llvm-svn: 187396
* Fix a truly egregious thinko in anonymous namespace check,Eric Christopher2013-07-291-2/+2
| | | | | | | | update testcase to make sure we generate debug info for walrus by adding a non-trivial constructor and verify that we don't emit an ODR signature for the type. llvm-svn: 187393
* Make sure we don't emit an ODR hash for types with no name and makeEric Christopher2013-07-291-2/+4
| | | | | | sure the comments for each testcase are a bit easier to distinguish. llvm-svn: 187392
* Elaborate a bit on the type unit and ODR conditional code.Eric Christopher2013-07-291-4/+4
| | | | llvm-svn: 187385
* Make file_status::getUniqueID const.Rafael Espindola2013-07-292-2/+2
| | | | llvm-svn: 187383
* Include st_dev to make the result of getUniqueID actually unique.Rafael Espindola2013-07-293-31/+21
| | | | | | This will let us use getUniqueID instead of st_dev directly on clang. llvm-svn: 187378
* [mips] Add comment and simplify function.Akira Hatanaka2013-07-291-23/+14
| | | | llvm-svn: 187371
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