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* R600/SI: Fix src1_modifiers for class instructionsMatt Arsenault2015-02-181-2/+26
| | | | | | | | src1 doesn't have modifiers, but the operand was missing resulting in an encoding build error when all fields are required.' llvm-svn: 229611
* R600/SI: Fix not setting clamp / omod for v_cndmask_b32_e64Matt Arsenault2015-02-182-3/+5
| | | | | | | Rename the multiclass since it now applies to the output modifiers as well. llvm-svn: 229610
* R600: Fix operand encoding errorMatt Arsenault2015-02-181-0/+1
| | | | llvm-svn: 229609
* R600/SI: Fix encoding error from glc bit on VI SMRD instructionsMatt Arsenault2015-02-181-1/+5
| | | | llvm-svn: 229608
* R600/SI: Fix operand encoding for flat instructionsMatt Arsenault2015-02-181-2/+4
| | | | llvm-svn: 229607
* R600/SI: Fix error from vdst on no return atomicsMatt Arsenault2015-02-181-3/+5
| | | | | | | Set the ignored field to 0 so we can enable noNamedPositionallyEncodedOperands. llvm-svn: 229606
* R600/SI: Add missing offset operand to buffer bothenMatt Arsenault2015-02-182-4/+4
| | | | llvm-svn: 229605
* R600/SI: Add missing soffset operand to global atomicsMatt Arsenault2015-02-181-2/+2
| | | | llvm-svn: 229604
* R600/SI: Fix brace identationMatt Arsenault2015-02-181-1/+1
| | | | llvm-svn: 229603
* Re-apply "InstrProf: Add unit tests for the profile reader and writer"Justin Bogner2015-02-182-14/+46
| | | | | | | | | | | | | | Have the InstrProfWriter return a MemoryBuffer instead of a std::string. This fixes the alignment issues the reader would hit, and it's a more appropriate type for this anyway. I've also removed an ugly helper function that's not needed since we're allowing initializer lists now, and updated some error code checks based on MSVC's issues with r229473. This reverts r229483, reapplying r229478. llvm-svn: 229602
* LiveRangeCalc: Rename some parameters from kill to use, NFC.Matthias Braun2015-02-183-36/+35
| | | | | | Those parameters did not necessarily describe kill points but just uses. llvm-svn: 229601
* Generalize getExtendAddRecStart to work with both sign and zeroSanjoy Das2015-02-181-143/+218
| | | | | | | | | | | extensions. This change also removes `DEBUG(dbgs() << "SCEV: untested prestart overflow check\n");` because that case has a unit test now. Differential Revision: http://reviews.llvm.org/D7645 llvm-svn: 229600
* Make the Mips AsmPrinter independent of global subtargetEric Christopher2015-02-182-11/+23
| | | | | | | | | | | | | | initialization. Initialize the subtarget once per function and migrate EmitStartOfAsmFile to either use calls on the TargetMachine or get information from the subtarget we'd use for assembling. The top-level-ness of the MIPS attribute output for assembly is, by nature, contrary to how we'd want to do this for an LTO situation where we have multiple cpu architectures so this solution is good enough for now. llvm-svn: 229596
* Unify selectMipsCPU implementations.Eric Christopher2015-02-183-20/+11
| | | | llvm-svn: 229595
* Bugfix: SCEV incorrectly marks certain expressions as nswSanjoy Das2015-02-181-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I could not come up with a test case for this one; but I don't think `getPreStartForSignExtend` can assume `AR` is `nsw` -- there is one place in scalar evolution that calls `getSignExtendAddRecStart(AR, ...)` without proving that `AR` is `nsw` (line 1564) OperandExtendedAdd = getAddExpr(WideStart, getMulExpr(WideMaxBECount, getZeroExtendExpr(Step, WideTy))); if (SAdd == OperandExtendedAdd) { // If AR wraps around then // // abs(Step) * MaxBECount > unsigned-max(AR->getType()) // => SAdd != OperandExtendedAdd // // Thus (AR is not NW => SAdd != OperandExtendedAdd) <=> // (SAdd == OperandExtendedAdd => AR is NW) const_cast<SCEVAddRecExpr *>(AR)->setNoWrapFlags(SCEV::FlagNW); // Return the expression with the addrec on the outside. return getAddRecExpr(getSignExtendAddRecStart(AR, Ty, this), getZeroExtendExpr(Step, Ty), L, AR->getNoWrapFlags()); } Differential Revision: http://reviews.llvm.org/D7640 llvm-svn: 229594
* Twines should be passed by const ref.Rafael Espindola2015-02-171-2/+2
| | | | llvm-svn: 229590
* [X86][FastIsel] Teach how to select scalar integer to float/double conversions.Andrea Di Biagio2015-02-171-0/+48
| | | | | | | | | | | | This patch teaches fast-isel how to select a (V)CVTSI2SSrr for an integer to float conversion, and how to select a (V)CVTSI2SDrr for an integer to double conversion. Added test 'fast-isel-int-float-conversion.ll'. Differential Revision: http://reviews.llvm.org/D7698 llvm-svn: 229589
* Add r228939 back with a fix.Rafael Espindola2015-02-173-11/+29
| | | | | | | | | | | | | The problem in the original patch was not switching back to .text after printing an eh table. Original message: On ELF, put PIC jump tables in a non executable section. Fixes PR22558. llvm-svn: 229586
* rename variables again because these tables also deal with stores; NFCSanjay Patel2015-02-171-31/+31
| | | | | | Suggestion by Simon Pilgrim llvm-svn: 229574
* IR: fieldIsMDNode() should be false for MDStringDuncan P. N. Exon Smith2015-02-171-8/+1
| | | | | | | Simplify the code. It has been a while since the schema has been so "flexible". llvm-svn: 229573
* AsmPrinter: Take range in DwarfExpression::AddExpression(), NFCDuncan P. N. Exon Smith2015-02-174-6/+11
| | | | | | | | | | Previously `DwarfExpression::AddExpression()` relied on default-constructing the end iterators for `DIExpression` -- once the operands are represented explicitly via `MDExpression` (instead of via the strange `StringRef` navigator in `DIHeaderIterator`) this won't work. Explicitly take an iterator for the end of the range. llvm-svn: 229572
* [X86][SSE] Generalised unpckl/unpckh shuffle matchingSimon Pilgrim2015-02-171-0/+24
| | | | | | | | Added commuted unpckl/unpckh shuffle matching patterns as many cases containing undefined lanes fail to commute by themselves. Differential Revision: http://reviews.llvm.org/D7564 llvm-svn: 229571
* Add comment to explain a non-obvious setting; NFC.Sanjay Patel2015-02-171-0/+6
| | | | | | | This is paraphrased from Simon Pilgrim's comment in: http://reviews.llvm.org/D7492 llvm-svn: 229566
* remove function names from comments; NFCSanjay Patel2015-02-171-38/+31
| | | | llvm-svn: 229558
* replace meaningless variable names; NFCISanjay Patel2015-02-171-31/+31
| | | | llvm-svn: 229549
* Add r228980 back.Rafael Espindola2015-02-175-23/+51
| | | | | | | | | | Add support for having multiple sections with the same name and comdat. Using this in combination with -ffunction-sections allows LLVM to output a .o file with mulitple sections named .text. This saves space by avoiding long unique names of the form .text.<C++ mangled name>. llvm-svn: 229541
* Add r228889 back.Rafael Espindola2015-02-171-31/+26
| | | | | | | | | | Original message: Invert the section relocation map. It now points from rel section to section. Use it to set sh_info, avoiding a brittle name lookup. llvm-svn: 229539
* Add r228888 back.Rafael Espindola2015-02-171-7/+3
| | | | | | | | Original message: Use the existing SymbolTableIndex instead of doing a lookup. NFC. llvm-svn: 229538
* Add r228886 back now that r229530 fixed the issue lldb was hitting.Rafael Espindola2015-02-171-47/+45
| | | | | | | | | | Original message: Create the Seciton -> Rel Section map when it is first needed. NFC. Saves a walk over every section. llvm-svn: 229536
* R600/SI: Fix asam errors in SIFoldOperandsTom Stellard2015-02-171-1/+2
| | | | | | | We were trying to fold into implicit uses, which led to out of bounds access of the MCInstrDesc::OpInfo arrray. llvm-svn: 229533
* prevent folding a scalar FP load into a packed logical FP instruction (PR22371)Sanjay Patel2015-02-173-16/+50
| | | | | | | | | | | | | | | | Change the memory operands in sse12_fp_packed_scalar_logical_alias from scalars to vectors. That's what the hardware packed logical FP instructions define: 128-bit memory operands. There are no scalar versions of these instructions...because this is x86. Generating the wrong code (folding a scalar load into a 128-bit load) is still possible using the peephole optimization pass and the load folding tables. We won't completely solve this bug until we either fix the lowering in fabs/fneg/fcopysign and any other places where scalar FP logic is created or fix the load folding in foldMemoryOperandImpl() to make sure it isn't changing the size of the load. Differential Revision: http://reviews.llvm.org/D7474 llvm-svn: 229531
* Don't deference the section_end() iterator.Rafael Espindola2015-02-171-0/+3
| | | | | | Hard to test given the undefined behavior nature. llvm-svn: 229530
* Make the ARM AsmPrinter independent of global subtargetEric Christopher2015-02-174-70/+93
| | | | | | | | | | | | | | | | | initialization. Initialize the subtarget once per function and migrate Emit{Start|End}OfAsmFile to either use attributes on the TargetMachine or get information from the subtarget we'd use for assembling. One bit (getISAEncoding) touched the general AsmPrinter and the debug output. Handle this one by passing the function for the subprogram down and updating all callers and users. The top-level-ness of the ARM attribute output for assembly is, by nature, contrary to how we'd want to do this for an LTO situation where we have multiple cpu architectures so this solution is good enough for now. llvm-svn: 229528
* 80-column fixups.Eric Christopher2015-02-172-8/+11
| | | | llvm-svn: 229527
* DIBuilder: add trackIfUnresolved() to all nodes that may be cyclic.Adrian Prantl2015-02-171-3/+14
| | | | | | | | Tested in clang/test/CodeGenObjCCXX/debug-info-cyclic.mm rdar://problem/19839612 llvm-svn: 229521
* [Object] Support reading 64-bit MIPS ELF archivesSimon Atanasyan2015-02-171-5/+25
| | | | | | | | | | | | | | | | | | | The 64-bit MIPS ELF archive file format is used by MIPS64 targets. The main difference from a regular archive file is the symbol table format: 1. ar_name is equal to "/SYM64/" 2. number of symbols and offsets are 64-bit integers http://techpubs.sgi.com/library/manuals/4000/007-4658-001/pdf/007-4658-001.pdf Page 96 The patch allows reading of such archive files by llvm-nm, llvm-objdump and other tools. But it does not support archive files with number of symbols and/or offsets exceed 2^32. I think it is a rather rare case requires more significant modification of `Archive` class code. http://reviews.llvm.org/D7546 llvm-svn: 229520
* Canonicalize splats as build_vectors (PR22283)Sanjay Patel2015-02-172-28/+22
| | | | | | | | | | | | | | | | | | | | | | This is a follow-on patch to: http://reviews.llvm.org/D7093 That patch canonicalized constant splats as build_vectors, and this patch removes the constant check so we can canonicalize all splats as build_vectors. This fixes the 2nd test case in PR22283: http://llvm.org/bugs/show_bug.cgi?id=22283 The unfortunate code duplication between SelectionDAG and DAGCombiner is discussed in the earlier patch review. At least this patch is just removing code... This improves an existing x86 AVX test and changes codegen in an ARM test. Differential Revision: http://reviews.llvm.org/D7389 llvm-svn: 229511
* R600/SI: Extend private extload pattern to include zext loadsTom Stellard2015-02-171-4/+6
| | | | llvm-svn: 229507
* Prefer SmallVector::append/insert over push_back loops.Benjamin Kramer2015-02-1727-159/+72
| | | | | | Same functionality, but hoists the vector growth out of the loop. llvm-svn: 229500
* Fixed a bug in store sinking.Elena Demikhovsky2015-02-171-4/+6
| | | | | | | | | | The problem was in store-sink barrier check. Store sink barrier should be checked for ModRef (read-write) mode. http://llvm.org/bugs/show_bug.cgi?id=22613 llvm-svn: 229495
* OrcJIT: Appease msc18 not to be confused on executeCompileCallback<OrcX86_64>.NAKAMURA Takumi2015-02-171-2/+3
| | | | llvm-svn: 229494
* Reformat.NAKAMURA Takumi2015-02-171-5/+3
| | | | llvm-svn: 229493
* [X86] Silence -Wsign-compare warnings.Andrea Di Biagio2015-02-171-2/+2
| | | | | | | | | GCC 4.8 reported two new warnings due to comparisons between signed and unsigned integer expressions. The new warnings were accidentally introduced by revision 229480. Added explicit casts to silence the warnings. No functional change intended. llvm-svn: 229488
* Revert "InstrProf: Add unit tests for the profile reader and writer"Justin Bogner2015-02-172-45/+14
| | | | | | | | | | This added API to the InstrProfWriter to write to a string so I could write unittests without using temp files. This doesn't really work, since the format has tighter alignment requirements than a char. This reverts r229478 and its follow-up, r229481. llvm-svn: 229483
* AVX-512: changes in intel_ocl_bi calling conventionsElena Demikhovsky2015-02-172-14/+33
| | | | | | | | - added mask types v8i1 and v16i1 to possible function parameters - enabled passing 512-bit vectors in standard CC - added a test for KNL intel_ocl_bi conventions llvm-svn: 229482
* [X86] Combine vector anyext + and into a vector zextMichael Kuperstein2015-02-171-9/+99
| | | | | | | | | | Vector zext tends to get legalized into a vector anyext, represented as a vector shuffle with an undef vector + a bitcast, that gets ANDed with a mask that zeroes the undef elements. Combine this into an explicit shuffle with a zero vector instead. This allows shuffle lowering to match it as a zext, instead of matching it as an anyext and emitting an explicit AND. This combine only covers a subset of the cases, but it's a start. Differential Revision: http://reviews.llvm.org/D7666 llvm-svn: 229480
* Re-apply "InstrProf: Add unit tests for the profile reader and writer"Justin Bogner2015-02-172-14/+45
| | | | | | | | Add these tests again, but use va_list instead of initializer lists. This reverts r229456, reapplying r229455. llvm-svn: 229478
* Make the PowerPC AsmPrinter independent of global subtargetEric Christopher2015-02-171-15/+24
| | | | | | | | | initialization. Initialize the subtarget once per function and migrate EmitStartOfAsmFile to either use attributes on the TargetMachine or get information from all of the various subtargets. llvm-svn: 229475
* Add a FIXME to move IsLittleEndian to the target machine.Eric Christopher2015-02-171-0/+1
| | | | llvm-svn: 229472
* Move ABI handling and 64-bitness to the PowerPC target machine.Eric Christopher2015-02-175-32/+42
| | | | | | | This required changing how the computation of the ABI is handled and how some of the checks for ABI/target are done. llvm-svn: 229471
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