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* [Mips] Add support for min/max/umin/umax atomicsMirko Brkusanin2019-12-126-28/+385
* [AArch64][SVE] Remove nxv1f32 and nxv1f64 as legal typesCullen Rhodes2019-12-123-31/+13
* Revert "[ARM][MVE] Sink vector shift operand"Sam Parker2019-12-122-28/+3
* [ARM][MVE] Sink vector shift operandSam Parker2019-12-122-3/+28
* [AArch64][SVE] Add patterns for scalable vselectCameron McInally2019-12-112-2/+12
* [IR] Split out target specific intrinsic enums into separate headersReid Kleckner2019-12-1146-19/+68
* Rename TTI::getIntImmCost for instructions and intrinsicsReid Kleckner2019-12-1113-39/+41
* Revert "[SDAG] remove use restriction in isNegatibleForFree() when called fro...Sanjay Patel2019-12-112-7/+4
* [WebAssembly] Add new `export_name` clang attribute for controlling wasm expo...Sam Clegg2019-12-114-1/+36
* Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=Off builds after D65958 and...Fangrui Song2019-12-111-0/+2
* Add intrinsics for unary narrowing operationsAndrzej Warzynski2019-12-112-8/+18
* [AArch64] Be more careful to skip debug operands in LdSt Optimizier.Florian Hahn2019-12-111-7/+10
* [SDAG] remove use restriction in isNegatibleForFree() when called from getNeg...Sanjay Patel2019-12-112-4/+7
* [AArch64] Skip debug ops with regsOverlap in AArch64 LD/ST opt.Florian Hahn2019-12-111-1/+1
* [X86] Erase dead LEA instruction after converting it to MOV in FixupLEAPass::...Craig Topper2019-12-111-0/+3
* [SystemZ] Fix 128-bit strict FMA expansion pre-z14Ulrich Weigand2019-12-111-6/+4
* Revert "[AArch64][SVE] Implement intrinsics for non-temporal loads & stores"Kerry McLaughlin2019-12-113-98/+2
* [AArch64] Teach Load/Store optimizier to rename store operands for pairing.Florian Hahn2019-12-111-8/+322
* [AArch64][SVE] Add DAG combine rules for gather loads and sext/zextAndrzej Warzynski2019-12-113-48/+204
* Revert "Reland [AArch64][MachineOutliner] Return address signing for outlined...Oliver Stannard2019-12-111-288/+8
* [AArch64][SVE] Implement intrinsics for non-temporal loads & storesKerry McLaughlin2019-12-113-2/+98
* [ARM][LowOverheadLoops] Remove dead loop update instructions.Sjoerd Meijer2019-12-111-2/+73
* [ARM][MVE] Add intrinsics for immediate shifts. (reland)Simon Tatham2019-12-111-20/+32
* [NFC][PowerPC] Remove the dead conditions in the if(cond)QingShan Zhang2019-12-111-5/+1
* [PowerPC] Exploitate the Vector Integer Average InstructionsQingShan Zhang2019-12-111-0/+19
* [X86] Split v64i1 arguments into 2 v32i1s that will be promoted to v32i8 unde...Craig Topper2019-12-101-3/+17
* [FPEnv][X86] Constrained FCmp intrinsics enabling on X86Wang, Pengfei2019-12-119-94/+252
* [X86] Go back to considering v64i1 as a legal type under min-legal-vector-wid...Craig Topper2019-12-101-47/+32
* [BPF] put not-section-attribute externs into BTF ".extern" data sectionYonghong Song2019-12-101-3/+6
* [RISCV] Improve assembler missing feature warningsSimon Cook2019-12-102-11/+33
* [ARM][MVE] Refactor complex vector intrinsics [NFCI]Mikhail Maltsev2019-12-102-197/+116
* [Alignment][NFC] CreateMemSet use MaybeAlignGuillaume Chatelet2019-12-101-3/+3
* [AArch64] Fix issues with large arrays on stackKiran Chandramohan2019-12-105-27/+26
* [AArch64][SVE] Add wide compare immediate patternsCullen Rhodes2019-12-101-0/+101
* [BPF] Support to emit debugInfo for extern variablesYonghong Song2019-12-093-15/+54
* [NFC] Add { } to silence compiler warning [-Wmissing-braces].Huihui Zhang2019-12-091-1/+1
* add support for strict operation fpextend/fpround/fsqrt on X86 backendLiu, Chen32019-12-104-94/+86
* Revert "[ARM][MVE] Add intrinsics for immediate shifts."Eric Christopher2019-12-091-32/+20
* [AArch64][SVE] Implement SPLAT_VECTOR for i1 vectors.Eli Friedman2019-12-091-13/+18
* [PowerPC] [NFC] Cleanup xxpermdi peephole optimizationJinsong Ji2019-12-091-109/+113
* [PGO][PGSO] Instrument the code gen / target passes.Hiroshi Yamauchi2019-12-093-2/+52
* [PowerPC][NFC] Rename ANDI(S)o8 to ANDI(S)8oJinsong Ji2019-12-097-26/+26
* [ARM][MVE][Intrinsics] Add VQADDQ, VHADDQ, VRHADDQ, VQSUBQ, VHSUBQ, VQDMULHQ,...Mark Murray2019-12-091-68/+184
* [ARM][MVE][Intrinsics] Add VMULL[BT]Q_(INT|POLY) intrinsics.Mark Murray2019-12-092-38/+96
* [PowerPC] Refactor FinishCall. [NFC]Sean Fertile2019-12-092-309/+341
* [ARM] Fix NEON failure introduced by D71065.Simon Tatham2019-12-091-3/+5
* [ARM][MVE] Add intrinsics for immediate shifts.Simon Tatham2019-12-091-22/+32
* [RISCV] Machine Operand Flag SerializationSam Elliott2019-12-093-13/+51
* [ARM][MVE] Add complex vector intrinsicsMikhail Maltsev2019-12-091-0/+178
* [ARM] Enable MVE masked loads and storesDavid Green2019-12-091-1/+1
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