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* [AArch64] Fix a silent codegen fault in BUILD_VECTOR lowering.James Molloy2014-10-171-9/+9
* [PowerPC] Enable use of lxvw4x/stxvw4x in VSX code generationBill Schmidt2014-10-172-3/+15
* Mips: Only set divrem i64 to custom on 64bitJan Vesely2014-10-171-2/+2
* [mips] Add support for COP1's Branch-On-Cond-Likely instructionsVasileios Kalintiris2014-10-171-2/+10
* [mips] Add support for COP0's Branch-On-Cond-Likely instructionsVasileios Kalintiris2014-10-171-6/+25
* ARM: Fix a bug which was causing convergence failure in constant-island pass.Akira Hatanaka2014-10-171-1/+6
* R600/SI: Simplify debug printingMatt Arsenault2014-10-171-5/+3
* R600/SI: Remove another VALU patternMatt Arsenault2014-10-161-5/+0
* Erase fence insertion from SelectionDAGBuilder.cpp (NFC)Robin Morisset2014-10-163-0/+15
* R600/SI: Remove unnecessary VALU patternsMatt Arsenault2014-10-161-41/+0
* R600: Fix nonsensical implementation of computeKnownBits for BFEMatt Arsenault2014-10-161-5/+1
* Delete -std-compile-opts.Rafael Espindola2014-10-161-22/+22
* [AArch64] Fix miscompile of sdiv-by-power-of-2.Juergen Ributzka2014-10-162-4/+3
* [mips] Account for endianess when expanding BuildPairF64/ExtractElementF64 no...Vasileios Kalintiris2014-10-161-1/+4
* [mips] Marked the DI/EI instruction aliases as MIPS32r2Vasileios Kalintiris2014-10-161-2/+2
* Test commit access: remove extra new line at the end of fileVasileios Kalintiris2014-10-161-1/+0
* R600: Remove dead functionMatt Arsenault2014-10-162-15/+0
* [AVX512] Add DQ subvector insertsAdam Nemet2014-10-152-11/+33
* [AVX512] Two new attributes in X86VectorVTInfo for subvector insertAdam Nemet2014-10-152-4/+14
* [AVX512] Rename arg from Opcode32/64 to Opcode128/256 in vinsert_for_sizeAdam Nemet2014-10-151-4/+4
* R600: Remove unnecessary part of computeKnownBitsForTargetNodeMatt Arsenault2014-10-151-5/+0
* Move variable down to useMatt Arsenault2014-10-151-4/+4
* R600/SI: Fix bug where immediates were being used in DS addr operandsTom Stellard2014-10-151-1/+4
* Wrong attribute. LLVM_ATTRIBUTE_UNUSED not LLVM_ATTRIBUTE_USEDSid Manning2014-10-151-1/+1
* Wrong attribute. LLVM_ATTRIBUTE_USED not LLVM_ATTRIBUTE_UNUSEDSid Manning2014-10-151-1/+1
* Add LLVM_ATTRIBUTE_UNUSED to function currently just used in an assertSid Manning2014-10-151-0/+2
* Reapply "[FastISel][AArch64] Add custom lowering for GEPs."Juergen Ributzka2014-10-151-0/+76
* [FastISel][AArch64] Factor out add with immediate emission into a helper func...Juergen Ributzka2014-10-151-13/+28
* Enable the instruction printer in HexagonMCTargetDescSid Manning2014-10-154-4/+64
* R600/SI: Also try to use 0 base for misaligned 8-byte DS loads.Matt Arsenault2014-10-151-0/+17
* R600: Fix miscompiles when BFE has multiple usesMatt Arsenault2014-10-151-7/+10
* Simplify handling of --noexecstack by using getNonexecutableStackSection.Rafael Espindola2014-10-1516-67/+36
* Move getNonexecutableStackSection up to the base ELF class.Rafael Espindola2014-10-156-23/+0
* R600: Use existing variableMatt Arsenault2014-10-151-1/+1
* R600: Remove outdated commentMatt Arsenault2014-10-151-3/+0
* Revert "[FastISel][AArch64] Add custom lowering for GEPs."Juergen Ributzka2014-10-151-85/+0
* ARM: drop check for triple that's no longer used.Tim Northover2014-10-151-3/+2
* Remove unused variable.Eric Christopher2014-10-151-1/+0
* [AArch64] Wrong CC access in CSINC-conditional branch sequenceGerolf Hoflehner2014-10-141-5/+1
* [AAarch64] Optimize CSINC-branch sequenceGerolf Hoflehner2014-10-142-29/+137
* [X86][SSE] pslldq/psrldq shuffle mask decodesSimon Pilgrim2014-10-143-0/+71
* ARM: remove ARM/Thumb distinction for preferred alignment.Tim Northover2014-10-141-5/+0
* ARM: allow misaligned local variables in Thumb1 mode.Tim Northover2014-10-141-3/+1
* [FastISel][AArch64] Add custom lowering for GEPs.Juergen Ributzka2014-10-141-0/+85
* [x86 asm] allow fwait alias in both At&t and Intel modes (PR21208)Hans Wennborg2014-10-141-1/+1
* ARM: set preferred aggregate alignment to 32 universally.Tim Northover2014-10-141-4/+3
* [FastISel][AArch64] Fix sign-/zero-extend folding when SelectionDAG is involved.Juergen Ributzka2014-10-141-39/+190
* Reapply "R600: Add new intrinsic to read work dimensions"Jan Vesely2014-10-143-5/+20
* Revert "R600: Add new intrinsic to read work dimensions"Rafael Espindola2014-10-143-20/+5
* R600: Add new intrinsic to read work dimensionsJan Vesely2014-10-143-5/+20
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