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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-10-17 00:36:20 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-10-17 00:36:20 +0000 |
| commit | bfaab76f6be9fa843fe702c5ff81d65260f64644 (patch) | |
| tree | 5f32b5b09c5f9971d34093a5415a9d4305d653b6 /llvm/lib/Target | |
| parent | 07df631129ee5464edaad7eea9e203d4a109f259 (diff) | |
| download | bcm5719-llvm-bfaab76f6be9fa843fe702c5ff81d65260f64644.tar.gz bcm5719-llvm-bfaab76f6be9fa843fe702c5ff81d65260f64644.zip | |
R600/SI: Simplify debug printing
llvm-svn: 219999
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/R600/SIFixSGPRCopies.cpp | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp index 349744c5b56..086b44433c2 100644 --- a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp @@ -243,7 +243,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { // we must move it to the VALU, because the SGPR operands will // all end up being assigned the same register, which means // there is a potential for a conflict if different threads take - // different control flow paths. + // different control flow paths. // // For Example: // @@ -305,8 +305,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { !hasVGPROperands(MI, TRI)) continue; - DEBUG(dbgs() << "Fixing REG_SEQUENCE:\n"); - DEBUG(MI.print(dbgs())); + DEBUG(dbgs() << "Fixing REG_SEQUENCE: " << MI); TII->moveToVALU(MI); break; @@ -318,8 +317,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { Src1RC = MRI.getRegClass(MI.getOperand(2).getReg()); if (TRI->isSGPRClass(DstRC) && (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) { - DEBUG(dbgs() << " Fixing INSERT_SUBREG:\n"); - DEBUG(MI.print(dbgs())); + DEBUG(dbgs() << " Fixing INSERT_SUBREG: " << MI); TII->moveToVALU(MI); } break; |
