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* [WebAssembly] Disable the store-results optimization.Dan Gohman2016-08-181-20/+0
| | | | | | | | | | The WebAssemly spec removing the return value from store instructions, so remove the associated optimization from LLVM. This patch leaves the store instruction operands in place for now, so stores now always write to "$drop"; these will be removed in a seperate patch. llvm-svn: 279100
* [AArch64][GlobalISel] Select floating-point binary ops.Ahmed Bougacha2016-08-182-0/+38
| | | | | | There is no FREM instruction, but the others are straightforward. llvm-svn: 279081
* [WebAssembly] Refactor WebAssemblyLowerEmscriptenException pass for ↵Derek Schuff2016-08-184-124/+182
| | | | | | | | | | | | | | | | | | | | | | setjmp/longjmp This patch changes the code structure of WebAssemblyLowerEmscriptenException pass to support both exception handling and setjmp/longjmp. It also changes the name of the pass and the source file. 1. Change the file/pass name to WebAssemblyLowerEmscriptenExceptions -> WebAssemblyLowerEmscriptenEHSjLj to make it clear that it supports both EH and SjLj 2. List function / global variable names at the top so they can be changed easily 3. Some cosmetic changes Patch by Heejin Ahn Differential Revision: https://reviews.llvm.org/D23588 llvm-svn: 279075
* [AArch64][GlobalISel] Select G_SDIV/G_UDIV.Ahmed Bougacha2016-08-182-1/+11
| | | | | | | | There is no REM instruction; that will require an expansion. It's not obvious that should be done in select, rather than as a (custom?) legalization. llvm-svn: 279074
* fix typo; NFCSanjay Patel2016-08-181-1/+1
| | | | llvm-svn: 279068
* [Hexagon] Create vcombine in HexagonCopyToCombineKrzysztof Parzyszek2016-08-181-18/+56
| | | | llvm-svn: 279067
* [mips] Correct tail call encoding for MIPSR6Simon Dardis2016-08-189-41/+31
| | | | | | | | | | | | | r277708 enabled tails calls for MIPS but used the 'jr' instruction when the jump target was held in a register. For MIPSR6, 'jalr $zero, $reg' should have been used. Additionally, add missing patterns for external and global symbols for tail calls. Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23301 llvm-svn: 279064
* Remove trailing whitespaceSimon Pilgrim2016-08-181-9/+9
| | | | llvm-svn: 279054
* [WebAssembly] Handle debug information and virtual registers without ↵Dominic Chen2016-08-173-3/+5
| | | | | | | | | | | | | | crashing (reland r278967) Summary: Currently, enabling debug information when compiling for WebAssembly crashes the backend. This commit fixes these by skipping debug values in backend passes. Reviewers: jfb, aprantl, dschuff, echristo Subscribers: llvm-commits, dschuff, jfb, MatzeB, dexonsmith, yurydelendik, mehdi_amini Differential Revision: https://reviews.llvm.org/D23635 llvm-svn: 279011
* Revert "[WebAssembly] Handle debug information and virtual registers without ↵Duncan P. N. Exon Smith2016-08-173-5/+3
| | | | | | | | | | crashing" This reverts commit r278967, since the new test is failing when you don't build the WebAssembly target (most people, since it's off-by-default). llvm-svn: 278973
* Replace a few more "fall through" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-1719-80/+119
| | | | | | Follow up to r278902. I had missed "fall through", with a space. llvm-svn: 278970
* GlobalISel: support irtranslation of icmp instructions.Tim Northover2016-08-171-0/+1
| | | | llvm-svn: 278969
* [WebAssembly] Handle debug information and virtual registers without crashingDominic Chen2016-08-173-3/+5
| | | | | | | | | | | | Summary: Currently, enabling debug information when compiling for WebAssembly crashes the backend. This commit fixes these by skipping debug values in backend passes. Reviewers: jfb, aprantl, dschuff, echristo Subscribers: mehdi_amini, yurydelendik, dexonsmith, MatzeB, jfb, dschuff, llvm-commits Differential Revision: https://reviews.llvm.org/D21808 llvm-svn: 278967
* AMDGPU: Remove dead optionMatt Arsenault2016-08-171-6/+0
| | | | llvm-svn: 278965
* [mips] Add l.[sd] and s.[sd] instruction aliasesSimon Dardis2016-08-171-0/+19
| | | | | | | | Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23121 llvm-svn: 278930
* [LoopStrenghtReduce] Refactoring and addition of a new target cost function.Jonas Paulsson2016-08-172-0/+24
| | | | | | | | | | | | | | | | | | | | | | | Refactored so that a LSRUse owns its fixups, as oppsed to letting the LSRInstance own them. This makes it easier to rate formulas for LSRUses, since the fixups are available directly. The Offsets vector has been removed since it was no longer necessary. New target hook isFoldableMemAccessOffset(), which is used during formula rating. For SystemZ, this is useful to express that loads and stores with float or vector types with a big/negative offset should be avoided in loops. Without this, LSR will generate a lot of negative offsets that would require extra instructions for loading the address. Updated tests: test/CodeGen/SystemZ/loop-01.ll Reviewed by: Quentin Colombet and Ulrich Weigand. https://reviews.llvm.org/D19152 llvm-svn: 278927
* Replace "fallthrough" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-1735-95/+116
| | | | | | | This is a mechanical change of comments in switches like fallthrough, fall-through, or fall-thru to use the LLVM_FALLTHROUGH macro instead. llvm-svn: 278902
* [ppc64] Don't apply sibling call optimization if callee has any byval argChuang-Yu Cheng2016-08-171-1/+8
| | | | | | | | | | | | | | | This is a quick work around, because in some cases, e.g. caller's stack size > callee's stack size, we are still able to apply sibling call optimization even callee has any byval arg. This patch fix: https://llvm.org/bugs/show_bug.cgi?id=28328 Reviewers: hfinkel kbarton nemanjai amehsan Subscribers: hans, tjablin https://reviews.llvm.org/D23441 llvm-svn: 278900
* [PM] Port the always inliner to the new pass manager in a much moreChandler Carruth2016-08-171-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | minimal and boring form than the old pass manager's version. This pass does the very minimal amount of work necessary to inline functions declared as always-inline. It doesn't support a wide array of things that the legacy pass manager did support, but is alse ... about 20 lines of code. So it has that going for it. Notably things this doesn't support: - Array alloca merging - To support the above, bottom-up inlining with careful history tracking and call graph updates - DCE of the functions that become dead after this inlining. - Inlining through call instructions with the always_inline attribute. Instead, it focuses on inlining functions with that attribute. The first I've omitted because I'm hoping to just turn it off for the primary pass manager. If that doesn't pan out, I can add it here but it will be reasonably expensive to do so. The second should really be handled by running global-dce after the inliner. I don't want to re-implement the non-trivial logic necessary to do comdat-correct DCE of functions. This means the -O0 pipeline will have to be at least 'always-inline,global-dce', but that seems reasonable to me. If others are seriously worried about this I'd like to hear about it and understand why. Again, this is all solveable by factoring that logic into a utility and calling it here, but I'd like to wait to do that until there is a clear reason why the existing pass-based factoring won't work. The final point is a serious one. I can fairly easily add support for this, but it seems both costly and a confusing construct for the use case of the always inliner running at -O0. This attribute can of course still impact the normal inliner easily (although I find that a questionable re-use of the same attribute). I've started a discussion to sort out what semantics we want here and based on that can figure out if it makes sense ta have this complexity at O0 or not. One other advantage of this design is that it should be quite a bit faster due to checking for whether the function is a viable candidate for inlining exactly once per function instead of doing it for each call site. Anyways, hopefully a reasonable starting point for this pass. Differential Revision: https://reviews.llvm.org/D23299 llvm-svn: 278896
* Some places that could using TargetParser in LLVM. NFC.Zijiao Ma2016-08-172-3/+8
| | | | llvm-svn: 278888
* ARM: Avoid dereferencing end() in ARMFrameLowering::emitPrologueDuncan P. N. Exon Smith2016-08-171-1/+2
| | | | | | | | llvm::tryFoldSPUpdateIntoPushPop assumes its arguments are valid MachineInstrs. Update ARMFrameLowering::emitPrologue to respect that; when LastPush==end(), it can't possibly be a push instruction anyway. llvm-svn: 278880
* Hexagon: Avoid dereferencing end() in HexagonInstrInfo::InsertBranchDuncan P. N. Exon Smith2016-08-171-7/+5
| | | | llvm-svn: 278878
* AMDGPU: Avoid looking for the DebugLoc in end()Duncan P. N. Exon Smith2016-08-171-14/+12
| | | | | | | The end() iterator isn't a safe thing to dereference. Pass the DebugLoc into EmitFetchClause and EmitALUClause to avoid it. llvm-svn: 278873
* [AMDGPU] Remove duplicate initialization of SIDebuggerInsertNops passKonstantin Zhuravlyov2016-08-161-1/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D23556 llvm-svn: 278863
* [x86] Allow merging multiple instances of an immediate within a basic block ↵Sanjay Patel2016-08-162-6/+9
| | | | | | | | | | | | | | for code size savings, for 64-bit constants. This patch handles 64-bit constants which can be encoded as 32-bit immediates. It extends the functionality added by https://reviews.llvm.org/D11363 for 32-bit constants to 64-bit constants. Patch by Sunita Marathe! Differential Revision: https://reviews.llvm.org/D23391 llvm-svn: 278857
* [AArch64] Adjust the scheduling model for Exynos M1.Evandro Menezes2016-08-161-14/+9
| | | | | | Refine the model for the FP division unit. llvm-svn: 278846
* [AArch64] Adjust the scheduling model for Exynos M1.Evandro Menezes2016-08-161-7/+11
| | | | | | Refine the model for the integer division unit. llvm-svn: 278845
* AMDGPU: Remove excessive padding from ImmOp and RegOp.Matt Arsenault2016-08-161-4/+4
| | | | | | | | | | | The structs ImmOp and RegOp are in AArch64AsmParser.cpp (inside anonymous namespace). This diff changes the order of fields and removes the excessive padding (8 bytes). Patch by Alexander Shaposhnikov llvm-svn: 278844
* [Hexagon] Standardize next batch of pseudo instructionsKrzysztof Parzyszek2016-08-1610-74/+67
| | | | | | | | | | | | | ALIGNA PS_aligna ALLOCA PS_alloca TFR_FI PS_fi TFR_FIA PS_fia TFR_PdFalse PS_false TFR_PdTrue PS_true VMULW PS_vmulw VMULW_ACC PS_vmulw_acc llvm-svn: 278832
* [mips] Enforce compact branch restrictionsSimon Dardis2016-08-161-13/+12
| | | | | | | | | | | Check both operands for use of the $zero register which cannot be used with a compact branch instruction. Reviewers: dsanders, vkalintris Differential Review: https://reviews.llvm.org/D23547 llvm-svn: 278824
* [Hexagon] Clean up some miscellaneous V60 intrinsics a bitKrzysztof Parzyszek2016-08-166-69/+58
| | | | llvm-svn: 278823
* [Hexagon] Standardize vector predicate load/store pseudo instructionsKrzysztof Parzyszek2016-08-163-67/+32
| | | | | | | | | | | | - Remove unused instructions: LDriq_pred_vec_V6, STriq_pred_vec_V6, and the 128B counterparts. - Rename: LDriq_pred_V6 PS_vloadrq_ai LDriq_pred_V6_128B PS_vloadrq_ai_128B STriq_pred_V6 PS_vstorerq_ai STriq_pred_V6_128B PS_vstorerq_ai_128B llvm-svn: 278813
* [AArch64][GlobalISel] Select G_MUL.Ahmed Bougacha2016-08-161-0/+37
| | | | llvm-svn: 278810
* [AArch64][GlobalISel] Factor out unsupported binop check. NFC.Ahmed Bougacha2016-08-161-40/+50
| | | | | | | We're going to need it for G_MUL, and, if other targets end up using something similar, we can easily put it in the generic selector. llvm-svn: 278808
* [AArch64][GlobalISel] Select (variable) shifts.Ahmed Bougacha2016-08-162-0/+19
| | | | | | For now, no support for immediates. llvm-svn: 278804
* [AArch64][GlobalISel] Select p0 G_FRAME_INDEX.Ahmed Bougacha2016-08-162-0/+20
| | | | | | And mark it as legal. llvm-svn: 278802
* [x86] Refactor a PowerPC specific ctlz/srl transformation (NFC).Pierre Gousseau2016-08-162-13/+7
| | | | | | | | Following the discussion on D22038, this refactors a PowerPC specific setcc -> srl(ctlz) transformation so it can be used by other targets. Differential Revision: https://reviews.llvm.org/D23445 llvm-svn: 278799
* [X86][SSE] Add support for combining v2f64 target shuffles to VZEXT_MOVL ↵Simon Pilgrim2016-08-161-3/+3
| | | | | | | | byte rotations The combine was only matching v2i64 as it assumed lowering to MOVQ - but we have v2f64 patterns that match in a similar fashion llvm-svn: 278794
* Correct the upper bound for a CBZ/CBNZ branch target.Prakhar Bahuguna2016-08-161-2/+4
| | | | | | | | | | | | | Summary: Fix for the upper bound check that was causing a build failure. Reviewers: olista01, rengolin, t.p.northover Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23501 llvm-svn: 278789
* [Thumb] Validate branch target for CBZ/CBNZ instructions.Prakhar Bahuguna2016-08-162-0/+11
| | | | | | | | | | | | | | | | | Summary: The assembler currently does not check the branch target for CBZ/CBNZ instructions, which only permit branching forwards with a positive offset. This adds validation for the branch target to ensure negative PC-relative offsets are not encoded into the instruction, whether specified as a literal or as an assembler symbol. Reviewers: rengolin, t.p.northover Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D23312 llvm-svn: 278788
* [X86][SSE] Add support for combining target shuffles to PALIGNR byte rotationsSimon Pilgrim2016-08-161-22/+55
| | | | llvm-svn: 278787
* [AVR] Fix compile errorsJob Noorman2016-08-162-5/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D23450 llvm-svn: 278784
* [X86] Add xgetbv/xsetbv intrinsics to non-windows platformsGuy Blank2016-08-163-3/+61
| | | | | | Differential Revision: https://reviews.llvm.org/D21958 llvm-svn: 278782
* [AMDGPU] Give enum an explicit 64-bit type to fix MSVC 2013 failuresReid Kleckner2016-08-151-1/+1
| | | | | | | | | | Recall that MSVC always gives enums the type 'int', nothing else. MSVC 2015 does not appear to have this problem anymore. Clang-cl -Wmicrosoft-enum-value flags this, FWIW, so now I have a true positive for my warning. :) llvm-svn: 278762
* AMDGPU/R600: Convert buffer id to VTX_READ inputJan Vesely2016-08-154-183/+110
| | | | | | | | | Use patterns instead of multiple instructions Add buffer id to asm string https://reviews.llvm.org/D22650 llvm-svn: 278749
* Revert "[Thumb] Validate branch target for CBZ/CBNZ instructions."Matthias Braun2016-08-152-11/+0
| | | | | | | | | | | This currently breaks the greendragon clang-stage1-configure-RA/ and brotli. It is probably just uncovering a pre-existing problem. Reverting temporarily to get the buildbots green again. A reduced testcase will follow shortly. This reverts commit r278659. llvm-svn: 278711
* AMDGPU: Update AMDGPURuntimeMetadata.h for enums of address space qualifiersYaxun Liu2016-08-151-0/+7
| | | | llvm-svn: 278682
* AMDGPU: Don't fold subregister extracts into tied operandsMatt Arsenault2016-08-151-3/+15
| | | | llvm-svn: 278676
* [AMDGPU] fix failure on printing of non-existing instruction operands.Valery Pykhtin2016-08-151-0/+5
| | | | | | Differential revision: https://reviews.llvm.org/D23323 llvm-svn: 278665
* MachineLoop: add methods findLoopControlBlock and findLoopPreheaderSjoerd Meijer2016-08-151-62/+11
| | | | | | | | | | | This adds two new utility functions findLoopControlBlock and findLoopPreheader to MachineLoop and MachineLoopInfo. These functions are refactored and taken from the Hexagon target as they are target independent; thus this is intendend to be a non-functional change. Differential Revision: https://reviews.llvm.org/D22959 llvm-svn: 278661
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