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* Default ISD::PREFETCH to expand.Evan Cheng2008-03-108-9/+2
| | | | llvm-svn: 48169
* Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.Evan Cheng2008-03-108-55/+18
| | | | llvm-svn: 48167
* fix 80 col violations.Chris Lattner2008-03-101-8/+8
| | | | llvm-svn: 48166
* Stylistic modifications. No functionality changes.Nicolas Geoffray2008-03-101-44/+39
| | | | llvm-svn: 48158
* Integer comparison tests for CellSPU.Scott Michel2008-03-104-75/+182
| | | | llvm-svn: 48152
* Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC'sScott Michel2008-03-1011-5/+45
| | | | | | | | return ValueType can depend its operands' ValueType. This is a cosmetic change, no functionality impacted. llvm-svn: 48145
* Add description of individual bits in CR. This fix PR1765.Nicolas Geoffray2008-03-105-38/+152
| | | | llvm-svn: 48143
* Allow insert_subreg into implicit, target-specific values. Christopher Lamb2008-03-108-18/+55
| | | | | | | Change insert/extract subreg instructions to be able to be used in TableGen patterns. Use the above features to reimplement an x86-64 pseudo instruction as a pattern. llvm-svn: 48130
* Increase ISD::ParamFlags to 64 bits. Increase the ByValSizeDale Johannesen2008-03-103-17/+28
| | | | | | | | | | field to 32 bits, thus enabling correct handling of ByVal structs bigger than 0x1ffff. Abstract interface a bit. Fixes gcc.c-torture/execute/pr23135.c and gcc.c-torture/execute/pr28982b.c in gcc testsuite (were ICE'ing on ppc32, quietly producing wrong code on x86-32.) llvm-svn: 48122
* Darwin PPC64 indirect call target goes in X12, not R12. This fixes theseChris Lattner2008-03-091-2/+3
| | | | | | | | two regression tests: test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll llvm-svn: 48120
* cell really does support cross-regclass moves, because R3 is in lots of ↵Chris Lattner2008-03-091-4/+9
| | | | | | different regclasses, and the code is not consistent when it comes to value tracking. llvm-svn: 48119
* make sure ar.pfs is in a register class, this fixes test/CodeGen/IA64/ret-0.llChris Lattner2008-03-091-3/+5
| | | | llvm-svn: 48118
* teach X86InstrInfo::copyRegToReg how to copy into ST(0) from Chris Lattner2008-03-091-1/+18
| | | | | | | | | | | | an RFP register class. Teach ScheduleDAG how to handle CopyToReg with different src/dst reg classes. This allows us to compile trivial inline asms that expect stuff on the top of x87-fp stack. llvm-svn: 48107
* add some code to support cross-register class copying from Chris Lattner2008-03-091-4/+22
| | | | | | RST -> RFP{32/64/80}. We only handle ST(0) for now. llvm-svn: 48104
* rearrange some code, no functionality change.Chris Lattner2008-03-091-58/+59
| | | | llvm-svn: 48101
* claim ST(x) registers are 80 bits, which is true. This doesn't affect Chris Lattner2008-03-091-1/+1
| | | | | | codegen yet because these can't be spilled (they don't exist until after RA). llvm-svn: 48098
* rename FP_SETRESULT -> FP_SET_ST0Chris Lattner2008-03-094-15/+15
| | | | llvm-svn: 48094
* rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support forChris Lattner2008-03-095-46/+62
| | | | | | | isel'ing value preserving FP roundings from one fp stack reg to another into a noop, instead of stack traffic. llvm-svn: 48093
* Finish implementing a readme entry: when inserting an i64 variableChris Lattner2008-03-092-43/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | into a vector of zeros or undef, and when the top part is obviously zero, we can just use movd + shuffle. This allows us to compile vec_set-B.ll into: _test3: movl $1234567, %eax andl 4(%esp), %eax movd %eax, %xmm0 ret instead of: _test3: subl $28, %esp movl $1234567, %eax andl 32(%esp), %eax movl %eax, (%esp) movl $0, 4(%esp) movq (%esp), %xmm0 addl $28, %esp ret llvm-svn: 48090
* add a noteChris Lattner2008-03-091-0/+37
| | | | llvm-svn: 48064
* Implement a readme entry, compilingChris Lattner2008-03-092-26/+51
| | | | | | | | | | | | | | #include <xmmintrin.h> __m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);} into: movl $1, %eax movd %eax, %xmm0 ret instead of a constant pool load. llvm-svn: 48063
* 1) Improve comments.Chris Lattner2008-03-081-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | 2) Don't try to insert an i64 value into the low part of a vector with movq on an x86-32 target. This allows us to compile: __m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);} into: _doload64: movaps LCPI1_0, %xmm0 ret instead of: _doload64: subl $28, %esp movl $0, 4(%esp) movl $1, (%esp) movq (%esp), %xmm0 addl $28, %esp ret llvm-svn: 48057
* minor simplifications to this code, don't create a deadChris Lattner2008-03-081-6/+10
| | | | | | SCALAR_TO_VECTOR on paths that end up not using it. llvm-svn: 48056
* This one looks easy, add a note.Chris Lattner2008-03-081-1/+2
| | | | llvm-svn: 48055
* move these to the appropriate fileChris Lattner2008-03-082-53/+57
| | | | llvm-svn: 48054
* More ppc32 byval handling (bug fixes). ThingsDale Johannesen2008-03-081-3/+23
| | | | | | are looking pretty good now. llvm-svn: 48043
* Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} ↵Evan Cheng2008-03-0810-13/+35
| | | | | | and prefetchnta instructions. llvm-svn: 48042
* Add support for calls with i128 return values on ppc64.Dan Gohman2008-03-081-3/+13
| | | | llvm-svn: 48041
* PPC64 passes arguments of integral type in i64 registers, not i32. Reflect thisBill Wendling2008-03-071-26/+43
| | | | | | | by promoting smaller integral values (i32 at this point) to i64, then truncating to get the wanted size. llvm-svn: 48030
* Add support for lowering 128-bit shifts on ppc64.Dan Gohman2008-03-071-44/+60
| | | | llvm-svn: 48029
* Next bits of PPC byval handling. Basically functionalDale Johannesen2008-03-071-7/+73
| | | | | | but there are bugs. llvm-svn: 48028
* Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).Chris Lattner2008-03-072-6/+16
| | | | llvm-svn: 48027
* Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to workChris Lattner2008-03-071-6/+3
| | | | | | with 32 or 64-bit operands/results. llvm-svn: 48026
* mark frem as expand for all legal fp types on x86, regardless of whetherChris Lattner2008-03-071-3/+2
| | | | | | we're using SSE or not. This fixes PR2122. llvm-svn: 48006
* some more spelling changesGabor Greif2008-03-061-1/+1
| | | | llvm-svn: 47996
* Refine Cell's i64 constant generation code to cover more constants where theScott Michel2008-03-061-7/+28
| | | | | | upper and lower 32-bits are the same (in addition to 0 and -1 previously.) llvm-svn: 47985
* gcc likes things spelled correctlyAndrew Lenharth2008-03-051-1/+1
| | | | llvm-svn: 47981
* Next bit of PPC ByVal handling; call-site code seemsDale Johannesen2008-03-051-3/+11
| | | | | | correct now. llvm-svn: 47978
* - Fix support for "special" i64 immediates that can be loadedScott Michel2008-03-054-647/+361
| | | | | | | | | | | using IL, ILA, et. al. v2i64 and i64 are now supported by the select bits (SELB) instruction. - Add missing comparison operations (testcase forthcoming) - More multiclass refactoring. llvm-svn: 47973
* evan implemented this.Chris Lattner2008-03-051-26/+0
| | | | llvm-svn: 47948
* isTwoAddress = 1 -> Constraints.Evan Cheng2008-03-051-47/+47
| | | | llvm-svn: 47941
* PSLLWri etc. are two-address instructions.Evan Cheng2008-03-051-1/+3
| | | | llvm-svn: 47940
* add a noteChris Lattner2008-03-051-0/+30
| | | | llvm-svn: 47939
* Ignore debugging related instructions if they get this far.Evan Cheng2008-03-051-0/+4
| | | | llvm-svn: 47934
* Rather than asserting. Dump out the MI that we are not able to encode and abort.Evan Cheng2008-03-051-1/+6
| | | | llvm-svn: 47933
* Add a target lowering hook to control whether it's worthwhile to compress fp ↵Evan Cheng2008-03-051-0/+10
| | | | | | | | constant. For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive. llvm-svn: 47931
* 64bit CAS on 32bit x86.Andrew Lenharth2008-03-053-8/+64
| | | | llvm-svn: 47929
* Refactor code. Remove duplicated functions that basically do the same thing asEvan Cheng2008-03-052-22/+9
| | | | | | findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies. llvm-svn: 47927
* Removed spurious EnablePPCRS check.Bill Wendling2008-03-041-4/+3
| | | | llvm-svn: 47918
* Move PPC lowering functions into PPCTargetLoweringDale Johannesen2008-03-042-28/+120
| | | | | | | class (cosmetic). First piece of byval implementation; this doesn't work yet. No functional change. llvm-svn: 47917
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