diff options
| author | Chris Lattner <sabre@nondot.org> | 2008-03-07 20:18:24 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2008-03-07 20:18:24 +0000 |
| commit | 20b5a2b0370b05acb88513481ec63924a3cc1b50 (patch) | |
| tree | 5bb0a5dc52bce97344b32b8db2a3583e5311bddf /llvm/lib/Target | |
| parent | 25ff7e217d2afb33f130ab524d2b8d9fffa5c8b2 (diff) | |
| download | bcm5719-llvm-20b5a2b0370b05acb88513481ec63924a3cc1b50.tar.gz bcm5719-llvm-20b5a2b0370b05acb88513481ec63924a3cc1b50.zip | |
Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).
llvm-svn: 48027
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.td | 6 |
2 files changed, 16 insertions, 6 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td index 4e6348d3991..e7b734f76b6 100644 --- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -289,13 +289,13 @@ def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2), def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), "sld $rA, $rS, $rB", IntRotateD, - [(set G8RC:$rA, (shl G8RC:$rS, GPRC:$rB))]>, isPPC64; + [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64; def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), "srd $rA, $rS, $rB", IntRotateD, - [(set G8RC:$rA, (srl G8RC:$rS, GPRC:$rB))]>, isPPC64; + [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64; def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), "srad $rA, $rS, $rB", IntRotateD, - [(set G8RC:$rA, (sra G8RC:$rS, GPRC:$rB))]>, isPPC64; + [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64; def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS), "extsb $rA, $rS", IntGeneral, @@ -579,6 +579,16 @@ def : Pat<(extloadi32 iaddr:$src), def : Pat<(extloadi32 xaddr:$src), (LWZX8 xaddr:$src)>; +// Standard shifts. These are represented separately from the real shifts above +// so that we can distinguish between shifts that allow 6-bit and 7-bit shift +// amounts. +def : Pat<(sra G8RC:$rS, GPRC:$rB), + (SRAD G8RC:$rS, GPRC:$rB)>; +def : Pat<(srl G8RC:$rS, GPRC:$rB), + (SRD G8RC:$rS, GPRC:$rB)>; +def : Pat<(shl G8RC:$rS, GPRC:$rB), + (SLD G8RC:$rS, GPRC:$rB)>; + // SHL/SRL def : Pat<(shl G8RC:$in, (i32 imm:$imm)), (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index a0f6ccc2b4c..963184ff204 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -81,9 +81,9 @@ def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift // amounts. These nodes are generated by the multi-precision shift code. -def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntBinOp>; -def PPCsra : SDNode<"PPCISD::SRA" , SDTIntBinOp>; -def PPCshl : SDNode<"PPCISD::SHL" , SDTIntBinOp>; +def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; +def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; +def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>; def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, |
