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authorChris Lattner <sabre@nondot.org>2008-03-07 20:13:51 +0000
committerChris Lattner <sabre@nondot.org>2008-03-07 20:13:51 +0000
commit25ff7e217d2afb33f130ab524d2b8d9fffa5c8b2 (patch)
treed9355b4967e7b5eea3697b423e705ba09968fa21 /llvm/lib/Target
parent910e9de13106bfaeb453340aaa7b4835f5893a04 (diff)
downloadbcm5719-llvm-25ff7e217d2afb33f130ab524d2b8d9fffa5c8b2.tar.gz
bcm5719-llvm-25ff7e217d2afb33f130ab524d2b8d9fffa5c8b2.zip
Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work
with 32 or 64-bit operands/results. llvm-svn: 48026
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.td9
1 files changed, 3 insertions, 6 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index a0b2512c6df..a0f6ccc2b4c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -20,9 +20,6 @@ include "PPCInstrFormats.td"
def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
SDTCisVT<0, f64>, SDTCisPtrTy<1>
]>;
-def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
- SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
-]>;
def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
SDTCisVT<1, i32> ]>;
@@ -84,9 +81,9 @@ def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
// amounts. These nodes are generated by the multi-precision shift code.
-def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
-def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
-def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
+def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntBinOp>;
+def PPCsra : SDNode<"PPCISD::SRA" , SDTIntBinOp>;
+def PPCshl : SDNode<"PPCISD::SHL" , SDTIntBinOp>;
def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
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