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| author | Chris Lattner <sabre@nondot.org> | 2008-03-07 06:36:32 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2008-03-07 06:36:32 +0000 |
| commit | d4defb00df2039f1480d1d6c6fc4c83e014e0e88 (patch) | |
| tree | 40af871bb6d2e0c77718117ce600cde8ea18d6d0 /llvm/lib/Target | |
| parent | 92e52c636fc04265434ce4583b4c9463f9060367 (diff) | |
| download | bcm5719-llvm-d4defb00df2039f1480d1d6c6fc4c83e014e0e88.tar.gz bcm5719-llvm-d4defb00df2039f1480d1d6c6fc4c83e014e0e88.zip | |
mark frem as expand for all legal fp types on x86, regardless of whether
we're using SSE or not. This fixes PR2122.
llvm-svn: 48006
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index d0d3f644583..22ddd832954 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -215,7 +215,9 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); + setOperationAction(ISD::FREM , MVT::f32 , Expand); setOperationAction(ISD::FREM , MVT::f64 , Expand); + setOperationAction(ISD::FREM , MVT::f80 , Expand); setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); setOperationAction(ISD::CTPOP , MVT::i8 , Expand); @@ -358,10 +360,8 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) // We don't support sin/cos/fmod setOperationAction(ISD::FSIN , MVT::f64, Expand); setOperationAction(ISD::FCOS , MVT::f64, Expand); - setOperationAction(ISD::FREM , MVT::f64, Expand); setOperationAction(ISD::FSIN , MVT::f32, Expand); setOperationAction(ISD::FCOS , MVT::f32, Expand); - setOperationAction(ISD::FREM , MVT::f32, Expand); // Expand FP immediates into loads from the stack, except for the special // cases we handle. @@ -398,7 +398,6 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) // We don't support sin/cos/fmod setOperationAction(ISD::FSIN , MVT::f32, Expand); setOperationAction(ISD::FCOS , MVT::f32, Expand); - setOperationAction(ISD::FREM , MVT::f32, Expand); // Special cases we handle for FP constants. addLegalFPImmediate(APFloat(+0.0f)); // xorps |
