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* MS asm: Properly handle quoted symbol namesDavid Majnemer2014-06-191-2/+4
* R600/SI: Add intrinsics for various math instructions.Matt Arsenault2014-06-198-13/+113
* Move ARMJITInfo off of the TargetMachine and down onto the subtarget.Eric Christopher2014-06-189-24/+28
* Use stdint macros for specifying size of constantsMatt Arsenault2014-06-181-2/+3
* R600: Handle fnearbyintMatt Arsenault2014-06-182-0/+13
* R600/SI: add gather4 and getlod intrinsics (v3)Marek Olsak2014-06-184-26/+175
* Use LL suffix for literal that should be 64-bits.Matt Arsenault2014-06-181-1/+1
* [PowerPC] Remove unnecessary load of r12 in indirect callUlrich Weigand2014-06-181-4/+0
* [ARM] [MC] Refactor the constant pool classesWeiming Zhao2014-06-181-136/+1
* R600: Expand vector fceilJan Vesely2014-06-181-0/+1
* [PowerPC] Simplify and improve loading into TOC registerUlrich Weigand2014-06-186-40/+25
* Work around ridiculous warning.Matt Arsenault2014-06-181-2/+5
* R600/SI: Add intrinsics for brev instructionsMatt Arsenault2014-06-186-1/+12
* R600/SI: Prettier operand printing for 64-bit ops.Matt Arsenault2014-06-182-14/+17
* [mips] SYNC $stype instruction was added in Mips32Matheus Almeida2014-06-181-1/+7
* R600: Implement f64 ftrunc, ffloor and fceil.Matt Arsenault2014-06-182-0/+111
* R600: Custom lower f64 frint for pre-CIMatt Arsenault2014-06-182-0/+27
* R600/SI: Temporary fix for f64 fnegMatt Arsenault2014-06-181-0/+4
* R600/SI: Comparisons set vcc.Matt Arsenault2014-06-182-105/+115
* [X86] AVX512: Add non-temporal storesAdam Nemet2014-06-181-0/+29
* [X86] AVX512: Specify compressed displacement for vmovntdqaAdam Nemet2014-06-181-1/+1
* [PowerPC] Do not use BLA with the 64-bit SVR4 ABIUlrich Weigand2014-06-181-7/+7
* [PowerPC] Fix emitting instruction pairs on LEUlrich Weigand2014-06-181-9/+37
* [mips] Fix expansion of memory operation if destination register is not a GPR.Matheus Almeida2014-06-181-4/+29
* [mips] Report correct location when "erroring" about the use of $at when it's...Matheus Almeida2014-06-181-6/+13
* [mips][mips64r6] Add BLTC and BLTUC instructionsZoran Jovanovic2014-06-182-6/+25
* [mips] Access $at only if necessary.Matheus Almeida2014-06-181-3/+6
* Add pattern for unsigned v4i32->v4f64 convert on AVX512.Cameron McInally2014-06-181-0/+4
* [mips] Update MipsAsmParser so that it's possible to handle immediates that s...Matheus Almeida2014-06-181-0/+2
* [mips] Implement alias for 'and' and 'or' instructions for all ISAs.Matheus Almeida2014-06-181-0/+4
* [mips] Remove the last usage of parseRegister from MipsAsmParser.Matheus Almeida2014-06-181-29/+33
* R600: Implement 64bit SRAJan Vesely2014-06-181-5/+7
* R600: Implement 64bit SRLJan Vesely2014-06-182-0/+41
* R600: Implement 64bit SHLJan Vesely2014-06-182-0/+42
* [AArch64] Fix a pattern match failure caused by creating improper CONCAT_VECTOR.Kevin Qin2014-06-181-27/+39
* Replace some assert(0)'s with llvm_unreachable.Craig Topper2014-06-1816-23/+24
* Allow X86FastIsel to cope with 64 bit absolute relocationsLouis Gerbarg2014-06-171-10/+12
* [FastISel][X86] Optimize predicates and fold CMP instructions.Juergen Ributzka2014-06-171-13/+109
* R600/SI: Make sure target flags are set on pseudo VOP3 instructionsTom Stellard2014-06-172-14/+14
* R600/SI: Match cttz_zero_undefMatt Arsenault2014-06-172-1/+6
* R600/SI: Match ctlz_zero_undefMatt Arsenault2014-06-173-3/+8
* R600: Use LDS and vectors for private memoryTom Stellard2014-06-1717-18/+661
* R600/SI: Add a pattern for llvm.AMDGPU.barrier.globalTom Stellard2014-06-173-1/+16
* SelectionDAG: Expand i64 = FP_TO_SINT i32Tom Stellard2014-06-171-0/+1
* R600/SI: Re-initialize the m0 register after using it for indirect addressingTom Stellard2014-06-171-37/+50
* [FastISel][X86] Fix previous refactoring commit (r211077)Juergen Ributzka2014-06-171-4/+4
* Fix memory leak of RegScavenger accidentally added in r211037.James Molloy2014-06-171-1/+3
* AArch64: estimate inline asm length during branch relaxationTim Northover2014-06-171-1/+7
* [FastISel][X86] Refactor the code to get the X86 condition from a helper func...Juergen Ributzka2014-06-163-96/+110
* Add load/store functionalityReed Kotler2014-06-161-7/+93
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