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* AMDGPU: Fix assembler subtarget predicate for gfx9Matt Arsenault2017-02-183-1/+13
| | | | | | This was accepting GFX9 instructions on VI. llvm-svn: 295557
* AMDGPU: Fix disassembly of aperture registersMatt Arsenault2017-02-181-0/+5
| | | | llvm-svn: 295555
* AMDGPU: Merge initial gfx9 supportMatt Arsenault2017-02-1818-41/+239
| | | | llvm-svn: 295554
* [AVX-512] Remove 128/256-bit masked fp max/min intrinsics. Upgrade them to ↵Craig Topper2017-02-181-8/+0
| | | | | | legacy unmasked intrinsics and select instructions. llvm-svn: 295543
* AMDGPU/R600: Assert on infinite loop in EmitClauseMarkersJan Vesely2017-02-181-3/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D29792 llvm-svn: 295539
* [AVR] Set UseIntegratedAssemblerDylan McKay2017-02-181-0/+1
| | | | llvm-svn: 295535
* AArch64LoadStoreOptimizer: Correctly clear kill flagsMatthias Braun2017-02-171-2/+4
| | | | | | | | | | | When promoting the Load of a Store-Load pair to a COPY all kill flags between the store and the load need to be cleared. rdar://30402435 Differential Revision: https://reviews.llvm.org/D30110 llvm-svn: 295512
* [PPC] Give unaligned memory access lower cost on processor that supports itGuozhi Wei2017-02-171-0/+4
| | | | | | | | | | | | Newer ppc supports unaligned memory access, it reduces the cost of unaligned memory access significantly. This patch handles this case in PPCTTIImpl::getMemoryOpCost. This patch fixes pr31492. Differential Revision: https://reviews.llvm.org/D28630 This is resubmit of r292680, which was reverted by r293092. The internal application failures were actually caused by a source code bug. llvm-svn: 295506
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-1718-116/+271
| | | | | | Reapply r295371 with a fix for the Windows bot failures. llvm-svn: 295504
* [X86] Simplify by pulling out valuetype. NFCI.Simon Pilgrim2017-02-171-2/+2
| | | | llvm-svn: 295502
* [X86][SSE] Add (V)MOVD folding pattern with zextloadi64i32 load node.Simon Pilgrim2017-02-172-0/+6
| | | | | | Fixes PRPR31309 llvm-svn: 295492
* AMDGPU: Fix crashes on invalid icmp/fcmp intrinsicsMatt Arsenault2017-02-171-5/+9
| | | | llvm-svn: 295489
* In Thumb1 mode, the custom lowering for ARMISD::CMPZ could never emit tADDi3Artyom Skrobov2017-02-171-17/+14
| | | | | | | | | | | | Reviewers: jmolloy, t.p.northover Reviewed By: t.p.northover Subscribers: t.p.northover, aemerson, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D30097 llvm-svn: 295478
* [AArch64] Add Cavium ThunderX supportJoel Jones2017-02-174-2/+413
| | | | | | | | | | | | | | This set of patches adds support for Cavium ThunderX ARM64 processors: * ThunderX * ThunderX T81 * ThunderX T83 * ThunderX T88 Patch by Stefan Teleman Differential Revision: https://reviews.llvm.org/D28891 llvm-svn: 295475
* [ARM] Replace HasT2ExtractPack with HasDSPSam Parker2017-02-176-136/+98
| | | | | | | | | | | Removed the HasT2ExtractPack feature and replaced its references with HasDSP. This then allows the Thumb2 extend instructions to be selected for ARMv8M +dsp. These instruction descriptions have also been refactored and more target tests have been added for their isel. Differential Revision: https://reviews.llvm.org/D29623 llvm-svn: 295452
* [ARM] GlobalISel: Clean up some helpersDiana Picus2017-02-171-19/+24
| | | | | | | Return invalid opcodes when some of the helpers in the instruction selection pass can't handle a given combination. llvm-svn: 295446
* [ARM] GlobalISel: Check mappings used by reg bank selectDiana Picus2017-02-171-21/+120
| | | | | | | | Add some asserts to make sure we're using the mappings that we think we're using. This is to keep us from accidentally breaking functionality while moving to TableGen'erated mappings. llvm-svn: 295441
* [ARM] GlobalISel: Use Subtarget in LegalizerDiana Picus2017-02-173-13/+11
| | | | | | | | Start using the Subtarget to make decisions about what's legal. In particular, we only mark floating point operations as legal if we have VFP2, which is something we should've done from the very start. llvm-svn: 295439
* Revert "[Hexagon] Start using regmasks on calls"Rafael Espindola2017-02-1718-270/+115
| | | | | | | | | | This reverts commit r295371. It broke windows bots: http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio llvm-svn: 295402
* Fix -Wunused-lambda-capture by removing some unused lambda capturesDavid Blaikie2017-02-161-2/+2
| | | | llvm-svn: 295373
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-1618-115/+270
| | | | | | All the cool targets are doing it... llvm-svn: 295371
* [RDF] Aggregate shadow phi uses into one cluster when propagating live infoKrzysztof Parzyszek2017-02-162-70/+68
| | | | llvm-svn: 295366
* AMDGPU: Remove llvm.AMDGPU.cube intrinsicMatt Arsenault2017-02-163-25/+1
| | | | llvm-svn: 295359
* AMDGPU: Remove llvm.AMDGPU.rsq intrinsicMatt Arsenault2017-02-162-6/+0
| | | | llvm-svn: 295358
* Re-apply r282920 "X86: Allow conditional tail calls in Win64 "leaf" ↵Hans Wennborg2017-02-162-6/+6
| | | | | | | | | | functions (PR26302)" The original commit was reverted in r283329 due to a miscompile in Chromium. That turned out to be the same issue as PR31257, which was fixed in r295262. llvm-svn: 295357
* [RDF] Differentiate between defining and clobbering nodesKrzysztof Parzyszek2017-02-164-13/+88
| | | | | | | | | | Defining nodes should not alias with one another, while clobbering nodes can. When pushing defs on stacks, push clobbers first, link non-clobbering defs, then push the defs. The data flow in a statement is now: uses -> clobbers -> defs. llvm-svn: 295356
* [RDF] Move normalize(RegisterRef) to PhysicalRegisterInfoKrzysztof Parzyszek2017-02-166-45/+36
| | | | | | Remove the duplicate from DFG and make some members of PRI private. llvm-svn: 295351
* x86 interrupt calling convention: only save xmm registers if the target ↵Andrea Di Biagio2017-02-162-2/+8
| | | | | | | | | | | | | | | | | | supports SSE The existing code always saves the xmm registers for 64-bit targets even if the target doesn't support SSE (which is common for kernels). Thus, the compiler inserts movaps instructions which lead to CPU exceptions when an interrupt handler is invoked. This commit fixes this bug by returning a register set without xmm registers from getCalleeSavedRegs and getCallPreservedMask for such targets. Patch by Philipp Oppermann. Differential Revision: https://reviews.llvm.org/D29959 llvm-svn: 295347
* [AArch64] AArch64AsmParser clean up of isImmediate functions. NFCSjoerd Meijer2017-02-162-144/+11
| | | | | | | | | | | Regression test neon-diagnostics.s needed changing because it now produces a more specific diagnostic about the immediate ranges. One change in the expected error message is not obvious, but there multiple candidate and it happens to pick the immediate diagnostic. Differential Revision: https://reviews.llvm.org/D29939 llvm-svn: 295331
* [WebAssembly] Add a cast to void to fix an unused private member warning, ↵Dan Gohman2017-02-161-1/+3
| | | | | | for now. llvm-svn: 295327
* [X86] Remove local areOnlyUsersOf helper and use SDNode::areOnlyUsersOf instead.Simon Pilgrim2017-02-161-9/+1
| | | | llvm-svn: 295326
* [ARM] GlobalISel: Select floating point loadsDiana Picus2017-02-161-10/+31
| | | | llvm-svn: 295321
* [ARM] GlobalISel: Select G_SEQUENCE and G_EXTRACTDiana Picus2017-02-161-0/+78
| | | | | | | | Since they're only used for passing around double precision floating point values into the general purpose registers, we'll lower them to VMOVDRR and VMOVRRD. llvm-svn: 295310
* [ARM] GlobalISel: Select double G_FADD and copiesDiana Picus2017-02-161-6/+29
| | | | | | Just use VADDD if available, bail out if not. llvm-svn: 295309
* [ARM] GlobalISel: Assert that we don't use the FPR bank if we don't have VFPDiana Picus2017-02-161-0/+12
| | | | llvm-svn: 295308
* [ARM] GlobalISel: Add reg bank mappings for G_SEQUENCE and G_EXTRACTDiana Picus2017-02-161-0/+26
| | | | | | | Support G_SEQUENCE and G_EXTRACT as needed for passing double precision floating point values in the soft-fp float mode. llvm-svn: 295306
* [ARM] GlobalISel: Make the FPR bank 64-bit wideDiana Picus2017-02-162-5/+22
| | | | | | | Also add mappings for single and double precision FP, and use them for G_FADD and G_LOAD. llvm-svn: 295302
* [ARM] GlobalISel: Legalize 64-bit G_FADD and G_LOADDiana Picus2017-02-161-0/+7
| | | | | | | | For now we just mark them as legal all the time and let the other passes bail out if they can't handle it. In the future, we'll want to move more of the brains into the legalizer. llvm-svn: 295300
* [ARM] GlobalISel: Lower double precision FP argsDiana Picus2017-02-161-6/+75
| | | | | | | | | | | | | | For the hard float calling convention, we just use the D registers. For the soft-fp calling convention, we use the R registers and move values to/from the D registers by means of G_SEQUENCE/G_EXTRACT. While doing so, we make sure to honor the endianness of the target, since the CCAssignFn doesn't do that for us. For pure soft float targets, we still bail out because we don't support the libcalls yet. llvm-svn: 295295
* [AVX-512] Remove masked packss/packus intrinsics and autoupgrade to unmasked ↵Craig Topper2017-02-161-12/+4
| | | | | | | | intrinsics with select instructions. For 512-bit add new unmasked intrinsics. The new 512-bit unmasked intrinsics will make it easy to handle these with the SSE/AVX intrinsics in InstCombine where we currently have a TODO. llvm-svn: 295290
* AMDGPU: Remove llvm.SI.sendmsgMatt Arsenault2017-02-162-6/+3
| | | | llvm-svn: 295270
* AMDGPU: Remove SI_fs_constant and SI_fs_interp intrinsicsMatt Arsenault2017-02-163-50/+3
| | | | | | Update test uses with expansion in terms of new intrinsics. llvm-svn: 295269
* [X86] Re-enable conditional tail calls and fix PR31257.Hans Wennborg2017-02-165-2/+156
| | | | | | | | | | | This reverts r294348, which removed support for conditional tail calls due to the PR above. It fixes the PR by marking live registers as implicitly used and defined by the now predicated tailcall. This is similar to how IfConversion predicates instructions. Differential Revision: https://reviews.llvm.org/D29856 llvm-svn: 295262
* GlobalISel: legalize va_arg on AArch64.Tim Northover2017-02-152-0/+85
| | | | | | | | Uses a Custom implementation because the slot sizes being a multiple of the pointer size isn't really universal, even for the architectures that do have a simple "void *" va_list. llvm-svn: 295255
* AMDGPU: Remove dead node definitionsMatt Arsenault2017-02-151-10/+0
| | | | llvm-svn: 295247
* AMDGPU: Consolidate sendmsg/sendmsghalt handling and testsMatt Arsenault2017-02-151-7/+4
| | | | llvm-svn: 295244
* AMDGPU: Replace assert with report_fatal_errorMatt Arsenault2017-02-151-1/+2
| | | | | | Also use a more refined condition. llvm-svn: 295239
* [X86][SSE] Don't call EltsFromConsecutiveLoads if any element is missing.Simon Pilgrim2017-02-151-4/+11
| | | | | | Minor performance speedup - if any call to getShuffleScalarElt fails to get a result, don't both calling for the remaining elements as EltsFromConsecutiveLoads will fail anyhow. llvm-svn: 295235
* [AArch64] Make am_ldrlit an iPTR - not OtherVT - operand. NFC-ish.Ahmed Bougacha2017-02-151-1/+1
| | | | | | | | | | | am_ldrlit diverged from am_brcond in r207105, but kept the OtherVT operand type. It made sense for branch targets, as those are represented as MVT::Other in SDAG. But loads operate on pointers. This shouldn't have an observable effect on any in-tree code, but helps make the patterns consistent for external users. llvm-svn: 295229
* [X86][SSE] Propagate undef upper elements from scalar_to_vector during ↵Simon Pilgrim2017-02-151-1/+7
| | | | | | | | shuffle combining Only do this for integer types currently - floats types (in particular insertps) load folding often fails with this. llvm-svn: 295208
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