diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-16 02:01:17 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-16 02:01:17 +0000 |
| commit | d3e5cb77e4cbba5966479c62d970eb28414995a2 (patch) | |
| tree | fbac4d061ad0590fddadd4e3cada9906879f4996 /llvm/lib/Target | |
| parent | d2c8a337aa58d449bb5513245ab017f93e51b404 (diff) | |
| download | bcm5719-llvm-d3e5cb77e4cbba5966479c62d970eb28414995a2.tar.gz bcm5719-llvm-d3e5cb77e4cbba5966479c62d970eb28414995a2.zip | |
AMDGPU: Remove llvm.SI.sendmsg
llvm-svn: 295270
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIIntrinsics.td | 2 |
2 files changed, 3 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index e14cf35a49a..a8af1bb98a8 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -2911,10 +2911,9 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, return DAG.getNode(Opc, DL, Op->getVTList(), Ops); } case Intrinsic::amdgcn_s_sendmsg: - case Intrinsic::amdgcn_s_sendmsghalt: - case AMDGPUIntrinsic::SI_sendmsg: { - unsigned NodeOp = (IntrinsicID == Intrinsic::amdgcn_s_sendmsghalt) ? - AMDGPUISD::SENDMSGHALT : AMDGPUISD::SENDMSG; + case Intrinsic::amdgcn_s_sendmsghalt: { + unsigned NodeOp = (IntrinsicID == Intrinsic::amdgcn_s_sendmsg) ? + AMDGPUISD::SENDMSG : AMDGPUISD::SENDMSGHALT; Chain = copyToM0(DAG, Chain, DL, Op.getOperand(3)); SDValue Glue = Chain.getValue(1); return DAG.getNode(NodeOp, DL, MVT::Other, Chain, diff --git a/llvm/lib/Target/AMDGPU/SIIntrinsics.td b/llvm/lib/Target/AMDGPU/SIIntrinsics.td index f98feeca430..5ea867c8fd0 100644 --- a/llvm/lib/Target/AMDGPU/SIIntrinsics.td +++ b/llvm/lib/Target/AMDGPU/SIIntrinsics.td @@ -64,8 +64,6 @@ let TargetPrefix = "SI", isTarget = 1 in { llvm_i32_ty], // tfe(imm) [IntrReadMem, IntrArgMemOnly]>; - def int_SI_sendmsg : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], []>; - // Fully-flexible SAMPLE instruction. class SampleRaw : Intrinsic < [llvm_v4f32_ty], // vdata(VGPR) |
