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| author | Diana Picus <diana.picus@linaro.org> | 2017-02-16 11:00:31 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2017-02-16 11:00:31 +0000 |
| commit | a93803b9fe8817607ce7be9c5ba8ce3b3611e8ee (patch) | |
| tree | 2188f470a0b86da7d2b644b8eac00426a6c0e9cd /llvm/lib/Target | |
| parent | f7de84ab9f0611dee1f07470afda5171055f325d (diff) | |
| download | bcm5719-llvm-a93803b9fe8817607ce7be9c5ba8ce3b3611e8ee.tar.gz bcm5719-llvm-a93803b9fe8817607ce7be9c5ba8ce3b3611e8ee.zip | |
[ARM] GlobalISel: Add reg bank mappings for G_SEQUENCE and G_EXTRACT
Support G_SEQUENCE and G_EXTRACT as needed for passing double precision floating
point values in the soft-fp float mode.
llvm-svn: 295306
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index 7af51c68b3a..193a85502e6 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -143,6 +143,32 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case G_FRAME_INDEX: OperandsMapping = getOperandsMapping({&ARM::ValueMappings[0], nullptr}); break; + case G_SEQUENCE: { + // We only support G_SEQUENCE for creating a double precision floating point + // value out of two GPRs. + LLT Ty1 = MRI.getType(MI.getOperand(1).getReg()); + LLT Ty2 = MRI.getType(MI.getOperand(3).getReg()); + if (Ty.getSizeInBits() != 64 || Ty1.getSizeInBits() != 32 || + Ty2.getSizeInBits() != 32) + return InstructionMapping{}; + OperandsMapping = + getOperandsMapping({&ARM::ValueMappings[6], &ARM::ValueMappings[0], + nullptr, &ARM::ValueMappings[0], nullptr}); + break; + } + case G_EXTRACT: { + // We only support G_EXTRACT for splitting a double precision floating point + // value into two GPRs. + LLT Ty1 = MRI.getType(MI.getOperand(1).getReg()); + LLT Ty2 = MRI.getType(MI.getOperand(2).getReg()); + if (Ty.getSizeInBits() != 32 || Ty1.getSizeInBits() != 32 || + Ty2.getSizeInBits() != 64) + return InstructionMapping{}; + OperandsMapping = + getOperandsMapping({&ARM::ValueMappings[0], &ARM::ValueMappings[0], + &ARM::ValueMappings[6], nullptr, nullptr}); + break; + } default: return InstructionMapping{}; } |

