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authorAhmed Bougacha <ahmed.bougacha@gmail.com>2017-02-15 20:38:31 +0000
committerAhmed Bougacha <ahmed.bougacha@gmail.com>2017-02-15 20:38:31 +0000
commitf8acf568f13d4c0b965ccaf7db55573fa0aee65e (patch)
tree63acd1c55a0c2339a702512d37075efba5e7d046 /llvm/lib/Target
parent360260066e52b3e4028deae8bf5157a72d428929 (diff)
downloadbcm5719-llvm-f8acf568f13d4c0b965ccaf7db55573fa0aee65e.tar.gz
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[AArch64] Make am_ldrlit an iPTR - not OtherVT - operand. NFC-ish.
am_ldrlit diverged from am_brcond in r207105, but kept the OtherVT operand type. It made sense for branch targets, as those are represented as MVT::Other in SDAG. But loads operate on pointers. This shouldn't have an observable effect on any in-tree code, but helps make the patterns consistent for external users. llvm-svn: 295229
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/AArch64/AArch64InstrFormats.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index cfc4dd24e96..e35d49bbd41 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -2454,7 +2454,7 @@ class PrefetchUI<bits<2> sz, bit V, bits<2> opc, string asm, list<dag> pat>
// Load literal address: 19-bit immediate. The low two bits of the target
// offset are implied zero and so are not part of the immediate.
-def am_ldrlit : Operand<OtherVT> {
+def am_ldrlit : Operand<iPTR> {
let EncoderMethod = "getLoadLiteralOpValue";
let DecoderMethod = "DecodePCRelLabel19";
let PrintMethod = "printAlignedLabel";
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