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* [X86] Remove execute permissions from a couple files.Craig Topper2017-09-212-0/+0
| | | | llvm-svn: 313863
* [X86] Remove windows line endings.Craig Topper2017-09-211-919/+919
| | | | llvm-svn: 313862
* [X86] Remove unused tablegen class.Craig Topper2017-09-211-7/+0
| | | | llvm-svn: 313861
* AMDGPU: Fix crash on immediate operandMatt Arsenault2017-09-211-1/+5
| | | | | | | | We can have a v_mac with an immediate src0. We can still fold if it's an inline immediate, otherwise it already uses the constant bus. llvm-svn: 313852
* [X86] Replace a condition that can never be true with an assert.Craig Topper2017-09-211-2/+2
| | | | llvm-svn: 313848
* [ARM] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-09-2017-233/+456
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 313823
* [NVPTX] Implemented shfl.sync instruction and supporting intrinsics/builtins.Artem Belevich2017-09-201-1/+73
| | | | | | Differential Revision: https://reviews.llvm.org/D38090 llvm-svn: 313820
* [mips] Fix calculation of a branch instruction offset to escape left shift ↵Simon Atanasyan2017-09-201-3/+3
| | | | | | of negative value llvm-svn: 313815
* AMDGPU: Start selecting v_mad_mixhi_f16Matt Arsenault2017-09-204-2/+97
| | | | llvm-svn: 313814
* X86: treat SwiftCC as Win64_CC on Win64Saleem Abdulrasool2017-09-201-0/+1
| | | | | | | | | | | The Swift CC is identical to Win64 CC with the exception of swift error being passed in r12 which is a CSR. However, since this calling convention is only used in swift -> swift code, it does not impact interoperability and can be treated entirely as Win64 CC. We would previously incorrectly lower the frame setup as we did not treat the frame as conforming to Win64 specifications. llvm-svn: 313813
* AMDGPU: Add tied operands to v_mad_mix{lo|hi}_f16Matt Arsenault2017-09-202-12/+23
| | | | | | | | | These write to the low and high half of the destination register and leave the other 16-bits unchanged. This is true for most 16-bit instructions on gfx9, but we don't use that now. llvm-svn: 313812
* Remove the default subtarget from the new Nios2 port. It's unused and ↵Eric Christopher2017-09-202-9/+1
| | | | | | deprecated. llvm-svn: 313808
* AMDGPU: Start selecting v_mad_mixlo_f16Matt Arsenault2017-09-202-0/+25
| | | | | | | | Also add some tests that should be able to use v_mad_mixhi_f16, but do not yet. This is trickier because we don't really model the partial update of the register done by 16-bit instructions. llvm-svn: 313806
* AMDGPU: Fix encoding of op_sel for mad_mix* opcodesMatt Arsenault2017-09-201-3/+3
| | | | llvm-svn: 313797
* CodeGen: support SwiftError SwiftCC on Windows x64Saleem Abdulrasool2017-09-201-0/+3
| | | | | | | | | | Add support for passing SwiftError through a register on the Windows x64 calling convention. This allows the use of swifterror attributes on parameters which is used by the swift front end for the `Error` parameter. This partially enables building the swift standard library for Windows x86_64. llvm-svn: 313791
* [X86][SSE] Remove unnecessary NonceMasks from combineX86ShufflesRecursively ↵Simon Pilgrim2017-09-201-25/+14
| | | | | | calls (NFCI) llvm-svn: 313743
* 'into' instruction should not be decoded as a valid instr in 64-bit modeAndrew V. Tischenko2017-09-201-1/+1
| | | | llvm-svn: 313735
* [X86] Remove isel checks for immediate size on floating point compare and ↵Craig Topper2017-09-203-36/+26
| | | | | | | | xop compare instructions. NFCI If these checks fail we end up not selecting an instruction at all. So we are already relying on the immediate being checked upstream of isel. So doing the check in isel is just bloat to the isel table. Interestingly, we didn't check on the AVX512 version of the instructions anyway. llvm-svn: 313724
* [AMDGPU] Fixed memory leak with inliner replacedStanislav Mekhanoshin2017-09-201-1/+3
| | | | | | Delete inliner before replacing it. llvm-svn: 313723
* AMDGPU: Move r600 only code into r600 only td fileMatt Arsenault2017-09-202-53/+54
| | | | llvm-svn: 313719
* [AMDGPU] Fix regression in test clang/test/CodeGen/backend-unsupported-error.llStanislav Mekhanoshin2017-09-201-1/+2
| | | | llvm-svn: 313718
* AMDGPU: Match load d16 hi instructionsMatt Arsenault2017-09-205-50/+161
| | | | | | | | | | | | Also starts selecting global loads for constant address in some cases. Some end up selecting to mubuf still, which requires investigation. We still get sub-optimal regalloc and extra waitcnts inserted due to not really tracking the liveness of the separate register halves. llvm-svn: 313716
* [AMDGPU] Port of HSAIL inlinerStanislav Mekhanoshin2017-09-205-1/+218
| | | | | | Differential Revision: https://reviews.llvm.org/D36849 llvm-svn: 313714
* AMDGPU: Cleanup load/store PatFragsMatt Arsenault2017-09-207-271/+244
| | | | | | Try to use a consistent naming scheme. llvm-svn: 313713
* AMDGPU: Match store d16_hi instructionsMatt Arsenault2017-09-204-18/+77
| | | | llvm-svn: 313712
* [ARM] Relax 'cpsie'/'cpsid' flag parsing.Jonathan Roelofs2017-09-191-1/+1
| | | | | | | | | | The ARM docs suggest in examples that the flags can have either case, and there are applications in the wild that (libopencm3, for example) that expect to be able to use the uppercase spelling. https://reviews.llvm.org/D37953 llvm-svn: 313680
* [MSP430] Align functions on 2-byte boundary instead of 4.Vadzim Dambrouski2017-09-191-1/+1
| | | | | | | | | | | | | | | | Summary: There is no benefit in having the 4-byte alignment, and removing this restriction can save a lot of space for some applications. Reviewers: asl, awygle Reviewed By: awygle Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36165 llvm-svn: 313676
* [AMDGPU] Prevent post-RA scheduler from breaking memory clausesStanislav Mekhanoshin2017-09-192-0/+58
| | | | | | | | | The pre-RA scheduler does load/store clustering, but post-RA scheduler undoes it. Add mutation to prevent it. Differential Revision: https://reviews.llvm.org/D38014 llvm-svn: 313670
* [SystemZ] Fix truncstore + bswap codegen bugUlrich Weigand2017-09-191-1/+2
| | | | | | | | | | | | | SystemZTargetLowering::combineSTORE contains code to transform a combination of STORE + BSWAP into a STRV type instruction. This transformation is correct for regular stores, but not for truncating stores. The routine neglected to check for that case. Fixes a miscompilation of llvm-objcopy with clang, which caused test suite failures in the SystemZ multistage build bot. llvm-svn: 313669
* [X86] Convert X86ISD::SELECT to ISD::VSELECT just before instruction ↵Craig Topper2017-09-193-22/+3
| | | | | | | | | | selection to avoid duplicate patterns Similar to what we do for X86ISD::SHRUNKBLEND just turn X86ISD::SELECT into ISD::VSELECT. This allows us to remove the duplicated TRUNC patterns. Differential Revision: https://reviews.llvm.org/D38022 llvm-svn: 313644
* [PowerPC Peephole] Constants into a join add, use ADDI over LI/ADD.Tony Jiang2017-09-191-0/+116
| | | | | | | | | | Two blocks prior to the join each perform an li and the the join block has an add using the initialized register. Optimize each predecessor block to instead use addi and delete the li's and add. Differential Revision: https://reviews.llvm.org/D36734 llvm-svn: 313639
* [Power9] Add missing Power9 instructions.Tony Jiang2017-09-195-442/+67
| | | | | | | The following 8 instructions are implemented in this patch. addpcis(subpcis, lnia), darn, maddhd, maddhdu, maddld, setb llvm-svn: 313636
* [globalisel] Add a G_BSWAP instruction and support bswap using it.Daniel Sanders2017-09-191-0/+3
| | | | llvm-svn: 313633
* [Nios2] Subtarget, basic infrastructure for frame, instructions and registersNikolai Bozhenov2017-09-1915-20/+545
| | | | | | | | | | | | | | This is the second minimal patch keeping Nios2 target buildable. I'm adding subtarget here and other stuff for frame lowering, instruction, register information methods. I do not add any test cases, as still there are missing parts like DAG selector and assembly printing. I plan to include them into the next patch. Patch by Andrei Grischenko <andrei.l.grischenko@intel.com> Differential Revision: https://reviews.llvm.org/D37256 llvm-svn: 313626
* [x86] Lowering Mask Set1 intrinsics to LLVM IRJina Nahias2017-09-191-24/+0
| | | | | | | | This patch, together with a matching clang patch (https://reviews.llvm.org/D37668), implements the lowering of X86 mask set1 intrinsics to IR. Differential Revision: https://reviews.llvm.org/D37669 llvm-svn: 313625
* [ARM] Use ADDCARRY / SUBCARRYRoger Ferrer Ibanez2017-09-192-20/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparatory step for D34515. This change: - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32 - lowering is done by first converting the boolean value into the carry flag using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two operations does the actual addition. - for subtraction, given that ISD::SUBCARRY second result is actually a borrow, we need to invert the value of the second operand and result before and after using ARMISD::SUBE. We need to invert the carry result of ARMISD::SUBE to preserve the semantics. - given that the generic combiner may lower ISD::ADDCARRY and ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering as well otherwise i64 operations now would require branches. This implies updating the corresponding test for unsigned. - add new combiner to remove the redundant conversions from/to carry flags to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C - fixes PR34045 - fixes PR34564 Differential Revision: https://reviews.llvm.org/D35192 llvm-svn: 313618
* AMDGPU: Run internalize symbols at -O0Matt Arsenault2017-09-191-21/+21
| | | | | | | | The relocations used for externally visible functions aren't supported, so the direct call emitted ends up hitting a linker error. llvm-svn: 313616
* [X86][Skylake] Adding the scheduling information for the SkylakeClient targetGadi Haber2017-09-193-3/+4014
| | | | | | | | | | | | | | This patch adds the instruction scheduling information for the SkylakeClient (SKL) architecture target by adding the file X86SchedSkylakeClient.td located under the X86 Target. We used the scheduling information retrieved from the Skylake architects in order to create the file. The scheduling information includes latency, number of micro-Ops and used ports by each SKL instruction. The patch continues the scheduling replacement and insertion effort started with the SNB target in r307529 and r310792 and for HSW in r311879. Please expect some performance fluctuations due to code alignment effects. Reviewers: craig.topper, zvi, chandlerc, igorb, aymanmus, RKSimon, delena Differential Revision: https://reviews.llvm.org/D37294 llvm-svn: 313613
* [X86] Remove some unnecessary patterns for truncate with X86ISD::SELECT and ↵Craig Topper2017-09-191-6/+0
| | | | | | | | undef preserved source. We canonicalize undef preserved sources to zero during intrinsic lowering. llvm-svn: 313612
* [X86] Add VPERMPD/VPERMQ and VPERMPS/VPERMD to the execution domain fixing ↵Craig Topper2017-09-191-0/+16
| | | | | | table. llvm-svn: 313610
* bpf: add inline-asm supportYonghong Song2017-09-184-0/+121
| | | | | | Signed-off-by: Yonghong Song <yhs@fb.com> Acked-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 313593
* [DAGCombiner] fold assertzexts separated by truncSanjay Patel2017-09-181-33/+0
| | | | | | | | | | | | | If we have an AssertZext of a truncated value that has already been AssertZext'ed, we can assert on the wider source op to improve the zext-y knowledge: assert (trunc (assert X, i8) to iN), i1 --> trunc (assert X, i1) to iN This moves a fold from being Mips-specific to general combining, and x86 shows improvements. Differential Revision: https://reviews.llvm.org/D37017 llvm-svn: 313577
* AMDGPU: Start selecting s_xnor_{b32, b64}Konstantin Zhuravlyov2017-09-183-2/+48
| | | | | | Differential Revision: https://reviews.llvm.org/D37981 llvm-svn: 313565
* [X86] Make sure we still emit zext for GR32 to GR64 when the source of the ↵Craig Topper2017-09-181-2/+4
| | | | | | | | | | | | zext is AssertZext The AssertZext we might see in this case is only giving information about the lower 32 bits. It isn't providing information about the upper 32 bits. So we should emit a zext. This fixes PR28540. Differential Revision: https://reviews.llvm.org/D37729 llvm-svn: 313563
* [X86] Don't emit COPY_TO_REG to ABCD registers before EXTRACT_SUBREG of sub_8bitCraig Topper2017-09-183-59/+7
| | | | | | | | This is similar to D37843, but for sub_8bit. This fixes all of the patterns except for the 2 that emit only an EXTRACT_SUBREG. That causes a verifier error with global isel because global isel doesn't know to issue the ABCD when doing this extract on 32-bits targets. Differential Revision: https://reviews.llvm.org/D37890 llvm-svn: 313558
* [X86] Don't emit COPY_TO_REG to ABCD registers before EXTRACT_SUBREG of ↵Craig Topper2017-09-182-56/+19
| | | | | | | | | | | | sub_8bit_hi I'm pretty sure that InstrEmitter::EmitSubregNode will take care of this itself by calling ConstrainForSubReg which in turn calls TRI->getSubClassWithSubReg. I think Jakob Stoklund Olesen alluded to this in his commit message for r141207 which added the code to EmitSubregNode. Differential Revision: https://reviews.llvm.org/D37843 llvm-svn: 313557
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-09-181-18/+57
| | | | | | Refine the model of FP loads and stores. llvm-svn: 313555
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-09-182-15/+84
| | | | | | | Refine the model of loads and stores using the register offset addressing modes. llvm-svn: 313554
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-09-181-1/+2
| | | | | | Fix formatting in the predicate function AArch64InstrInfo::isExynosShiftLeftFast(). llvm-svn: 313553
* [X86][AVX] Improve (i8 bitcast (v8i1 x)) handling for 256-bit vector compare ↵Simon Pilgrim2017-09-181-1/+1
| | | | | | | | results. As commented on D37849, AVX1 targets were missing a chance to use vmovmskps for v8f32/v8i32 results for bool vector bitcasts llvm-svn: 313547
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