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| author | Craig Topper <craig.topper@intel.com> | 2017-09-21 00:18:48 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-09-21 00:18:48 +0000 |
| commit | e33755860de4404edc09452e1461a986b9f2980c (patch) | |
| tree | 518376fb09fa482edf85386e1370b58b1feaac00 /llvm/lib/Target | |
| parent | f0ba3003329a7ba9cc60a81b315e8d306afa8c42 (diff) | |
| download | bcm5719-llvm-e33755860de4404edc09452e1461a986b9f2980c.tar.gz bcm5719-llvm-e33755860de4404edc09452e1461a986b9f2980c.zip | |
[X86] Replace a condition that can never be true with an assert.
llvm-svn: 313848
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 6cdaefd462a..f647c5de472 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -17673,8 +17673,8 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { if (Subtarget.hasAVX512()) { SDValue Cmp = DAG.getNode(X86ISD::FSETCCM, DL, MVT::v1i1, CondOp0, CondOp1, DAG.getConstant(SSECC, DL, MVT::i8)); - return DAG.getNode(VT.isVector() ? X86ISD::SELECT : X86ISD::SELECTS, - DL, VT, Cmp, Op1, Op2); + assert(!VT.isVector() && "Not a scalar type?"); + return DAG.getNode(X86ISD::SELECTS, DL, VT, Cmp, Op1, Op2); } SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1, |
