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| author | Craig Topper <craig.topper@intel.com> | 2017-09-19 17:19:45 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-09-19 17:19:45 +0000 |
| commit | 75370b9b49399a5487c94421e48a9f8720d844f3 (patch) | |
| tree | aada6920aadc3e37a1016e5be4362897a4120f62 /llvm/lib/Target | |
| parent | 50105d294241f2cd45b38c4304dda4f7df11abee (diff) | |
| download | bcm5719-llvm-75370b9b49399a5487c94421e48a9f8720d844f3.tar.gz bcm5719-llvm-75370b9b49399a5487c94421e48a9f8720d844f3.zip | |
[X86] Convert X86ISD::SELECT to ISD::VSELECT just before instruction selection to avoid duplicate patterns
Similar to what we do for X86ISD::SHRUNKBLEND just turn X86ISD::SELECT into ISD::VSELECT. This allows us to remove the duplicated TRUNC patterns.
Differential Revision: https://reviews.llvm.org/D38022
llvm-svn: 313644
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 6 |
3 files changed, 3 insertions, 22 deletions
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index aa09be2b24e..bec812bedfa 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -2414,8 +2414,9 @@ void X86DAGToDAGISel::Select(SDNode *Node) { ReplaceNode(Node, getGlobalBaseReg()); return; + case X86ISD::SELECT: case X86ISD::SHRUNKBLEND: { - // SHRUNKBLEND selects like a regular VSELECT. + // SHRUNKBLEND selects like a regular VSELECT. Same with X86ISD::SELECT. SDValue VSelect = CurDAG->getNode( ISD::VSELECT, SDLoc(Node), Node->getValueType(0), Node->getOperand(0), Node->getOperand(1), Node->getOperand(2)); diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 2b1d6cd7332..10012a88a30 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -7564,7 +7564,7 @@ multiclass avx512_cvtps2ph<X86VectorVTInfo _dest, X86VectorVTInfo _src, "vcvtps2ph", "$src2, $src1", "$src1, $src2", (X86cvtps2ph (_src.VT _src.RC:$src1), (i32 imm:$src2)), - NoItinerary, 0, 0, X86select>, AVX512AIi8Base; + NoItinerary, 0, 0>, AVX512AIi8Base; def mr : AVX512AIi8<0x1D, MRMDestMem, (outs), (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2), "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", @@ -8083,20 +8083,6 @@ multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode, (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>, EVEX, T8XS; - // for intrinsic patter match - def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask, - (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))), - DestInfo.ImmAllZerosV)), - (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask , - SrcInfo.RC:$src1)>; - - def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask, - (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))), - DestInfo.RC:$src0)), - (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0, - DestInfo.KRCWM:$mask , - SrcInfo.RC:$src1)>; - let mayStore = 1, mayLoad = 1, hasSideEffects = 0, ExeDomain = DestInfo.ExeDomain in { def mr : AVX512XS8I<opc, MRMDestMem, (outs), diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td index ca3d78dd7f2..b5f3033b3cd 100644 --- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td +++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td @@ -262,12 +262,6 @@ def X86testnm : SDNode<"X86ISD::TESTNM", SDTX86Testm, [SDNPCommutative]>; def X86movmsk : SDNode<"X86ISD::MOVMSK", SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>>; -def X86select : SDNode<"X86ISD::SELECT", - SDTypeProfile<1, 3, [SDTCVecEltisVT<1, i1>, - SDTCisSameAs<0, 2>, - SDTCisSameAs<2, 3>, - SDTCisSameNumEltsAs<0, 1>]>>; - def X86selects : SDNode<"X86ISD::SELECTS", SDTypeProfile<1, 3, [SDTCisVT<1, v1i1>, SDTCisSameAs<0, 2>, |
