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* [RISCV] implement li pseudo instructionAlex Bradbury2018-04-179-49/+266
| | | | | | | | | | | | | | The implementation follows the MIPS backend and expands the pseudo instruction directly during asm parsing. As the result, only real MC instructions are emitted to the MCStreamer. Additionally, PseudoLI instructions are emitted during codegen. The actual expansion to real instructions is performed during MI to MC lowering and is similar to the expansion performed by the GNU Assembler. Differential Revision: https://reviews.llvm.org/D41949 Patch by Mario Werner. llvm-svn: 330224
* [XRay] Typed event logging intrinsicKeith Wyss2018-04-173-352/+912
| | | | | | | | | | | | | | | | | | | | | Summary: Add an LLVM intrinsic for type discriminated event logging with XRay. Similar to the existing intrinsic for custom events, but also accepts a type tag argument to allow plugins to be aware of different types and semantically interpret logged events they know about without choking on those they don't. Relies on a symbol defined in compiler-rt patch D43668. I may wait to submit before I can see demo everything working together including a still to come clang patch. Reviewers: dberris, pelikan, eizan, rSerge, timshen Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45633 llvm-svn: 330219
* [WebAssembly] Add an assertion for an invalid CFGHeejin Ahn2018-04-171-0/+3
| | | | | | | | | | | | | | | Summary: It was not easy to provide a test case for D45648 (rL330079) because the bug didn't manifest itself in the set of currently valid IRs. Added an assertion to check this faster, thanks to @dblaikie's suggestion. Reviewers: dblaikie Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits, dblaikie Differential Revision: https://reviews.llvm.org/D45711 llvm-svn: 330217
* [WebAssembly] Teach fast-isel to gracefully recover from illegal return types.Dan Gohman2018-04-171-2/+6
| | | | | | Fixes PR36564. llvm-svn: 330215
* [X86] Add separate scheduling class for PSADBW instruction.Craig Topper2018-04-1713-22/+18
| | | | llvm-svn: 330204
* [X86] Remove unnecessary InstRW overrides. Add somes FIXMEs/TODOs.Craig Topper2018-04-175-98/+17
| | | | llvm-svn: 330203
* [Hexagon] Do not merge initializers for stack and non-stack expressionsKrzysztof Parzyszek2018-04-171-2/+42
| | | | | | | | | Stack addressing needs addressing modes that provide an offset field immediately following the frame index. An initializer from a non-stack addressing could force the stack address to use a form that does not provide an offset field. llvm-svn: 330191
* [X86] Add FP comparison scheduler classesSimon Pilgrim2018-04-1713-315/+105
| | | | | | | | Split VCMP/VMAX/VMIN instructions off to WriteFCmp and VCOMIS instructions off to WriteFCom instead of assuming they match WriteFAdd Differential Revision: https://reviews.llvm.org/D45656 llvm-svn: 330179
* [RISCV] Fix assert message operatorMandeep Singh Grang2018-04-161-1/+1
| | | | | | | | | | | | | | | | Summary: Specifying assert message with an || operator makes the compiler interpret it as a bool. Changed it to &&. Reviewers: asb, apazos Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, llvm-commits Differential Revision: https://reviews.llvm.org/D45660 llvm-svn: 330148
* [Hexagon] Turn off flag enabling auto-vectorizationKrzysztof Parzyszek2018-04-161-1/+1
| | | | | | It was turned on for testing and was accidentally left on in the commit. llvm-svn: 330139
* [NFC] Move verificaiton check for f128 conversion into LowerINT_TO_FP()Lei Huang2018-04-161-24/+14
| | | | | | | Move veriication check for legal conversions to f128 into LowerINT_TO_FP() and fix some indentations to match other sections of the code for readability. llvm-svn: 330138
* [AMDGPU][MC][VI][GFX9] Added support of SDWA/DPP for v_cndmask_b32Dmitry Preobrazhensky2018-04-162-1/+27
| | | | | | | | | See bug 36356: https://bugs.llvm.org/show_bug.cgi?id=36356 Differential Revision: https://reviews.llvm.org/D45446 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 330123
* [AArch64][SVE] Asm: Support for structured LD4 (scalar+imm) load instructions.Sander de Smalen2018-04-166-3/+68
| | | | | | | | | | | | Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45624 llvm-svn: 330120
* [AArch64][SVE] Asm: Support for structured LD3 (scalar+imm) load instructions.Sander de Smalen2018-04-166-3/+69
| | | | | | | | | | | | Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45623 llvm-svn: 330116
* [mips] Restrict certain trap instructions for micromipsr6Stefan Maksimovic2018-04-161-8/+14
| | | | | | | | | Instructions removed from micromipsr6: teqi, tgei, tgeiu, tlti, tltiu, tnei Differential Revision: https://reviews.llvm.org/D45318 llvm-svn: 330114
* [X86] Introduce archs: goldmont-plus & tremontGabor Buella2018-04-162-13/+43
| | | | | | | | | | | | | | | Using Goldmont's cost tables for these two upcoming atom archs. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45612 llvm-svn: 330109
* [AArch64][SVE] Asm: Support for structured LD2 (scalar+imm) load instructions.Sander de Smalen2018-04-166-4/+102
| | | | | | | | | | | | Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45622 llvm-svn: 330108
* [X86] Use uint32_t instead of unsigned in GetLo32XForm for readability. NFCCraig Topper2018-04-151-1/+1
| | | | | | GetLo8XForm right next to it uses uint8_t so uint32_t is consistent. llvm-svn: 330104
* [X86][MMX] Set PAVG/PHADD/PMIN/PMAX/PSIGN instructions to use same scheduler ↵Simon Pilgrim2018-04-141-12/+12
| | | | | | classes as SSE/AVX llvm-svn: 330085
* [NFC] fix trivial typos in document and commentsHiroshi Inoue2018-04-142-2/+2
| | | | | | "not not" -> "not" etc llvm-svn: 330083
* [WebAssembly] Fix a bug in MachineBasicBlock::findDebugLoc() callHeejin Ahn2018-04-141-3/+4
| | | | | | | | | | | | | | Summary: InsertPos is within the bacic block `Header`, so `findDebugLoc()` should be called on not `MBB` but `Header` instead. Reviewers: yurydelendik Subscribers: jfb, dschuff, aprantl, sbc100, jgravelle-google, sunfish, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D45648 llvm-svn: 330079
* [X86] Add the bizarro movsww and movzww mnemonics for the disassembler.Craig Topper2018-04-131-0/+20
| | | | | | | | The destination size of the movzx/movsx instruction is controlled by the normal operand size mechanisms. Only the input type is fixed. This means that a 0x66 prefix on the encoding for zext/sext 16->32 should really produce a 16->16 instruction. Functionally this is equivalent to a GR16->GR16 move since bits 16 and above will be preserved. So nothing is actually extended. llvm-svn: 330078
* MachO: trap unreachable instructionsTim Northover2018-04-133-1/+8
| | | | | | | Debugability is more important than saving 4 bytes to let us to fall through to nonense. llvm-svn: 330073
* [Hexagon] Initial instruction cost model for auto-vectorizationKrzysztof Parzyszek2018-04-132-98/+195
| | | | llvm-svn: 330065
* Revert r329956, "AArch64: Introduce a DAG combine for folding offsets into ↵Peter Collingbourne2018-04-132-68/+15
| | | | | | | | | | addresses." Caused a hang and eventually an assertion failure in LTO builds of 7zip-benchmark on aarch64 iOS targets. http://green.lab.llvm.org/green/job/lnt-ctmark-aarch64-O3-flto/2024/ llvm-svn: 330063
* [LV] Introduce TTI::getMinimumVFKrzysztof Parzyszek2018-04-132-0/+5
| | | | | | | | | | | The function getMinimumVF(ElemWidth) will return the minimum VF for a vector with elements of size ElemWidth bits. This value will only apply to targets for which TTI::shouldMaximizeVectorBandwidth returns true. The value of 0 indicates that there is no minimum VF. Differential Revision: https://reviews.llvm.org/D45271 llvm-svn: 330062
* [Power9] Add the TLS store instructions to the Power 9 modelStefan Pintilie2018-04-132-2/+2
| | | | | | | | | | | The Power 9 scheduler model should now include the TLS instructions. We can now, once again, mark the model as complete. From now on, if instructions are added to Power 9 but are not added to the model the build should produce an error. Hopefully that will alert the developer who is adding new instructions that they should also be added to the scheulder model. llvm-svn: 330060
* [mips] Materialize constants for multiplicationSimon Dardis2018-04-131-3/+76
| | | | | | | | | | | | | | | | | | | | | | | Previously, the MIPS backend would alwyas break down constant multiplications into a series of shifts, adds, and subs. This patch changes that so the cost of doing so is estimated. The cost is estimated against worst case constant materialization and retrieving the results from the HI/LO registers. For cases where the value type of the multiplication is not legal, the cost of legalization is estimated and is accounted for before performing the optimization of breaking down the constant This resolves PR36884. Thanks to npl for reporting the issue! Reviewers: abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D45316 llvm-svn: 330037
* [X86] Remove remaining itinerary support from instructions and target (PR37093)Simon Pilgrim2018-04-133-13/+0
| | | | llvm-svn: 330035
* [ARM] FP16 vmaxnm/vminnm scalar instructionsSjoerd Meijer2018-04-133-2/+20
| | | | | | | | | This adds code generation support for the FP16 vmaxnm/vminnm scalar instructions. Differential Revision: https://reviews.llvm.org/D44675 llvm-svn: 330034
* [ARC] Add LImm support for J/JLYan Luo2018-04-131-5/+17
| | | | llvm-svn: 330031
* [X86] Generalize X86FixupLEAs to work with TargetSchedModelSimon Pilgrim2018-04-131-3/+4
| | | | | | Similar to rL329834, don't rely on itinerary scheduler model to determine latencies for LEA thresholds, use the generic TargetSchedModel::computeInstrLatency call. llvm-svn: 330030
* Remove comment reference to itineraries. NFCI.Simon Pilgrim2018-04-131-1/+1
| | | | llvm-svn: 330025
* [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+imm) load instructionsSander de Smalen2018-04-133-0/+64
| | | | | | | | | | | | Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45618 llvm-svn: 330024
* [X86][AVX512] UNPCKL/H PS and PD should be scheduled with WriteFShuffle not ↵Simon Pilgrim2018-04-131-2/+2
| | | | | | WriteFAdd llvm-svn: 330023
* [X86] Remove remaining OpndItins/SizeItins from all instruction defs (PR37093)Simon Pilgrim2018-04-132-1715/+1301
| | | | llvm-svn: 330022
* Remove comment references to itineraries. NFCI.Simon Pilgrim2018-04-133-4/+4
| | | | llvm-svn: 330021
* Remove out of data comment. NFCI.Simon Pilgrim2018-04-131-2/+1
| | | | llvm-svn: 330019
* [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.Sander de Smalen2018-04-133-1/+107
| | | | | | | | | | | | | | | | | | | | Summary: Added instructions for contiguous stores, ST1, with scalar+imm addressing modes and corresponding tests. The patch also adds parsing of 'mul vl' as needed for the VL-scaled immediate. This is patch [6/6] in a series to add assembler/disassembler support for SVE's contiguous ST1 (scalar+imm) instructions. Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45432 llvm-svn: 330014
* [X86] Remove OpndItins/SizeItins from all sse instruction defs (PR37093)Simon Pilgrim2018-04-132-622/+566
| | | | llvm-svn: 330013
* [NEON] Support intrinsic for scalar and vector versions of the VRINTN ↵Ivan A. Kosarev2018-04-131-1/+1
| | | | | | | | instruction Differential Revision: https://reviews.llvm.org/D45514 llvm-svn: 330011
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-04-134-4/+4
| | | | | | "the the" -> "the", "we we" -> "we", etc llvm-svn: 330006
* [AArch64][SVE] Asm: Add support for parsing and printing SVE vector lists.Sander de Smalen2018-04-133-2/+78
| | | | | | | | | | | | | | | | | | | Summary: Added Z_(b|h|s|d) vector list RegisterOperands along with support to add/print the vector lists. This is patch [5/6] in a series to add assembler/disassembler support for SVE's contiguous ST1 (scalar+imm) instructions. Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: fhahn Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45431 llvm-svn: 330000
* [X86] Introduce cldemote instructionGabor Buella2018-04-134-0/+11
| | | | | | | | | | | | | | Hint to hardware to move the cache line containing the address to a more distant level of the cache without writing back to memory. Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45256 llvm-svn: 329992
* [X86] Remove the pmuldq/pmuldq intrinsics and replace with native IR.Craig Topper2018-04-131-18/+0
| | | | | | | | This completes the work started in r329604 and r329605 when we changed clang to no longer use the intrinsics. We lost some InstCombine SimplifyDemandedBit optimizations through this change as we aren't able to fold 'and', bitcast, shuffle very well. llvm-svn: 329990
* [X86] Remove unused MoveLoadStoreItins/ShiftOpndItins schedule class wrappers.Simon Pilgrim2018-04-122-36/+14
| | | | | | Was being used to move around empty/unused itineraries... llvm-svn: 329970
* [X86] Remove x86 InstrItinClass entries (PR37093)Simon Pilgrim2018-04-123-241/+94
| | | | | | This removes the last of the x86 schedule itineraries, I'm intending to cleanup the remaining uses of NoItinerary/OpndItins/etc. before resolving PR37093. llvm-svn: 329967
* AArch64: Introduce a DAG combine for folding offsets into addresses.Peter Collingbourne2018-04-122-15/+68
| | | | | | | | | | | This is a code size win in code that takes offseted addresses frequently, such as C++ constructors that typically need to compute an offseted address of a vtable. This reduces the size of Chromium for Android's .text section by 108KB. Differential Revision: https://reviews.llvm.org/D45199 llvm-svn: 329956
* [X86] Remove InstrItinClass entries from all x86 instruction defs (PR37093)Simon Pilgrim2018-04-123-318/+284
| | | | llvm-svn: 329953
* [X86] Remove InstrItinClass entries from SSE/AVX instructions defs (PR37093)Simon Pilgrim2018-04-122-521/+498
| | | | llvm-svn: 329945
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