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| author | Stefan Maksimovic <stefan.maksimovic@mips.com> | 2018-04-16 09:22:20 +0000 |
|---|---|---|
| committer | Stefan Maksimovic <stefan.maksimovic@mips.com> | 2018-04-16 09:22:20 +0000 |
| commit | 86d638ecdf1d4235872188a2143b9ccb7497ec15 (patch) | |
| tree | 963fe341d75a63ca5e0cdae07849eada00fd5765 /llvm/lib/Target | |
| parent | 14b6637edc41125997bf395f1a3504e7288b0e93 (diff) | |
| download | bcm5719-llvm-86d638ecdf1d4235872188a2143b9ccb7497ec15.tar.gz bcm5719-llvm-86d638ecdf1d4235872188a2143b9ccb7497ec15.zip | |
[mips] Restrict certain trap instructions for micromipsr6
Instructions removed from micromipsr6:
teqi, tgei, tgeiu, tlti, tltiu, tnei
Differential Revision: https://reviews.llvm.org/D45318
llvm-svn: 330114
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index 3e26464162e..5ab3e9b4a9a 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -971,16 +971,22 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm4, II_TLTU>, TEQ_FM_MM<0x28>; def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm4, II_TNE>, TEQ_FM_MM<0x30>; - - def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM_MM<0x0e>; - def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM_MM<0x09>; +} +let DecoderNamespace = "MicroMips" in { + def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM_MM<0x0e>, + ISA_MICROMIPS32_NOT_MIPS32R6; + def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM_MM<0x09>, + ISA_MICROMIPS32_NOT_MIPS32R6; def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>, - TEQI_FM_MM<0x0b>; - def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM_MM<0x08>; + TEQI_FM_MM<0x0b>, ISA_MICROMIPS32_NOT_MIPS32R6; + def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM_MM<0x08>, + ISA_MICROMIPS32_NOT_MIPS32R6; def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>, - TEQI_FM_MM<0x0a>; - def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM_MM<0x0c>; - + TEQI_FM_MM<0x0a>, ISA_MICROMIPS32_NOT_MIPS32R6; + def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM_MM<0x0c>, + ISA_MICROMIPS32_NOT_MIPS32R6; +} +let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { /// Load-linked, Store-conditional def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>; def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>; |
