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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-04-13 15:34:26 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-04-13 15:34:26 +0000 |
| commit | 834f7dc7abada8e8b10cc323ea296464771e9a94 (patch) | |
| tree | 6e1366925f3925526560ffc83973a080d9d29976 /llvm/lib/Target | |
| parent | 8ec047713680ee605106dbcd8ae3e23ad63aac22 (diff) | |
| download | bcm5719-llvm-834f7dc7abada8e8b10cc323ea296464771e9a94.tar.gz bcm5719-llvm-834f7dc7abada8e8b10cc323ea296464771e9a94.zip | |
[ARM] FP16 vmaxnm/vminnm scalar instructions
This adds code generation support for the FP16 vmaxnm/vminnm scalar
instructions.
Differential Revision: https://reviews.llvm.org/D44675
llvm-svn: 330034
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrNEON.td | 13 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrVFP.td | 4 |
3 files changed, 20 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 7f0222019f2..1e032640c55 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -527,6 +527,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, setOperationAction(ISD::BITCAST, MVT::i16, Custom); setOperationAction(ISD::BITCAST, MVT::i32, Custom); setOperationAction(ISD::BITCAST, MVT::f16, Custom); + + setOperationAction(ISD::FMINNUM, MVT::f16, Legal); + setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); } for (MVT VT : MVT::vector_valuetypes()) { @@ -1147,6 +1150,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, if (Subtarget->hasNEON()) { // vmin and vmax aren't available in a scalar form, so we use // a NEON instruction with an undef lane instead. + setOperationAction(ISD::FMINNAN, MVT::f16, Legal); + setOperationAction(ISD::FMAXNAN, MVT::f16, Legal); setOperationAction(ISD::FMINNAN, MVT::f32, Legal); setOperationAction(ISD::FMAXNAN, MVT::f32, Legal); setOperationAction(ISD::FMINNAN, MVT::v2f32, Legal); diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index 8757520c10c..fa2b83581f7 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -6870,6 +6870,17 @@ class N3VSPat<SDNode OpNode, NeonI Inst> (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>; +class N3VSPatFP16<SDNode OpNode, NeonI Inst> + : NEONFPPat<(f16 (OpNode HPR:$a, HPR:$b)), + (EXTRACT_SUBREG + (v4f16 (COPY_TO_REGCLASS (Inst + (INSERT_SUBREG + (v4f16 (COPY_TO_REGCLASS (v4f16 (IMPLICIT_DEF)), DPR_VFP2)), + HPR:$a, ssub_0), + (INSERT_SUBREG + (v4f16 (COPY_TO_REGCLASS (v4f16 (IMPLICIT_DEF)), DPR_VFP2)), + HPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>; + class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst> : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))), (EXTRACT_SUBREG @@ -6912,6 +6923,8 @@ def : N3VSMulOpPat<fmul, fsub, VFMSfd>, Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>; def : N2VSPat<fabs, VABSfd>; def : N2VSPat<fneg, VNEGfd>; +def : N3VSPatFP16<fmaxnan, VMAXhd>, Requires<[HasFullFP16]>; +def : N3VSPatFP16<fminnan, VMINhd>, Requires<[HasFullFP16]>; def : N3VSPat<fmaxnan, VMAXfd>, Requires<[HasNEON]>; def : N3VSPat<fminnan, VMINfd>, Requires<[HasNEON]>; def : NVCVTFIPat<fp_to_sint, VCVTf2sd>; diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td index 34945a23c03..98b780f1459 100644 --- a/llvm/lib/Target/ARM/ARMInstrVFP.td +++ b/llvm/lib/Target/ARM/ARMInstrVFP.td @@ -482,9 +482,9 @@ defm VSELVS : vsel_inst<"vs", 0b01, 6>; multiclass vmaxmin_inst<string op, bit opc, SDNode SD> { let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in { def H : AHbInp<0b11101, 0b00, opc, - (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), + (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), NoItinerary, !strconcat(op, ".f16\t$Sd, $Sn, $Sm"), - []>, + [(set HPR:$Sd, (SD HPR:$Sn, HPR:$Sm))]>, Requires<[HasFullFP16]>; def S : ASbInp<0b11101, 0b00, opc, |
