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* Add sanity checking for invalid register encodings for saturating instructions.Johnny Chen2011-04-071-0/+5
| | | | llvm-svn: 129096
* Add some more comments about checkings of invalid register numbers.Johnny Chen2011-04-071-0/+5
| | | | | | And two test cases. llvm-svn: 129090
* Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal ↵Tanya Lattner2011-04-071-0/+6
| | | | | | vector type (vectors of size 3). Also included test cases. llvm-svn: 129074
* Sanity check MSRi for invalid mask values and reject it as invalid.Johnny Chen2011-04-071-0/+5
| | | | | | rdar://problem/9246844 llvm-svn: 129050
* The ARM disassembler was not recognizing USADA8 instruction. Need to add ↵Johnny Chen2011-04-071-3/+5
| | | | | | | | | | checking for register values for USAD8 and USADA8. rdar://problem/9247060 llvm-svn: 129047
* Change -arm-divmod-libcall to a target neutral option.Evan Cheng2011-04-072-6/+7
| | | | llvm-svn: 129045
* Should also check SMLAD for invalid register values.Johnny Chen2011-04-071-6/+12
| | | | | | rdar://problem/9246650 llvm-svn: 129042
* Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for ↵Owen Anderson2011-04-061-1/+8
| | | | | | folded comparisons, just like ADD and SUB. llvm-svn: 129038
* Cleanups from Jim: remove redundant constraints and a dead FIXME.Owen Anderson2011-04-061-11/+5
| | | | llvm-svn: 129036
* Tidy up.Jim Grosbach2011-04-061-2/+1
| | | | llvm-svn: 129034
* A8.6.393Johnny Chen2011-04-061-26/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | The ARM disassembler should reject invalid (type, align) encodings as invalid instructions. So, instead of: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- vst2.32 {d0, d2}, [r3, :256], r3 we now have: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- mc-input.txt:1:1: warning: invalid instruction encoding 0xb3 0x9 0x3 0xf4 ^ llvm-svn: 129033
* A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"Johnny Chen2011-04-061-1/+14
| | | | | | | | | | Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits specified, if coproc == 10 or 11, we should reject the insn as invalid. rdar://problem/9239922 rdar://problem/9239596 llvm-svn: 129027
* Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.Johnny Chen2011-04-062-1/+3
| | | | | | | | | Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000, in class NVLaneOp. rdar://problem/9240648 llvm-svn: 129015
* Add another case we are not optimizing.Rafael Espindola2011-04-061-0/+30
| | | | llvm-svn: 129012
* The original issue has been fixed by not doing unnecessary sign extensions.Rafael Espindola2011-04-061-14/+17
| | | | | | Change the test to force a sign extension and expose the problem again. llvm-svn: 129011
* Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.Johnny Chen2011-04-061-7/+3
| | | | | | | | | | Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25}) is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid. rdar://problem/9239347 rdar://problem/9239467 llvm-svn: 128977
* Reapply r128946 (pseudoization of various instructions), and fix the extra ↵Owen Anderson2011-04-052-65/+42
| | | | | | imp-def of CPSR it was adding. llvm-svn: 128965
* Fix a typo in the handling of PKHTB opcode, plus add sanity check for ↵Johnny Chen2011-04-051-1/+7
| | | | | | | | | | illegal register encodings for DisassembleArithMiscFrm(). rdar://problem/9238659 llvm-svn: 128958
* Clean up some code for clarity.Bob Wilson2011-04-051-5/+24
| | | | llvm-svn: 128953
* Revert r128946 while I figure out why it broke the buildbots.Owen Anderson2011-04-052-38/+64
| | | | llvm-svn: 128951
* A7.3 register encodingJohnny Chen2011-04-051-0/+10
| | | | | | | | | | | | | Qd -> bit[12] == 0 Qn -> bit[16] == 0 Qm -> bit[0] == 0 If one of these bits is 1, the instruction is UNDEFINED. rdar://problem/9238399 rdar://problem/9238445 llvm-svn: 128949
* Give RSBS and RSCS the pseudo treatment.Owen Anderson2011-04-052-64/+38
| | | | llvm-svn: 128946
* ARM disassembler was erroneously accepting an invalid RSC instruction.Johnny Chen2011-04-051-0/+6
| | | | | | | | Added checks for regs which should not be 15. rdar://problem/9237734 llvm-svn: 128945
* ARM disassembler was erroneously accepting an invalid LSL instruction.Johnny Chen2011-04-051-0/+4
| | | | | | | | | For register-controlled shifts, we should check that the encoding constraint Inst{7} = 0 and Inst{4} = 1 is satisfied. rdar://problem/9237693 llvm-svn: 128941
* Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as ↵Owen Anderson2011-04-053-80/+76
| | | | | | doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions. llvm-svn: 128940
* The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.Johnny Chen2011-04-051-7/+19
| | | | | | | | Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change. rdar://problem/9236873 llvm-svn: 128922
* ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.Johnny Chen2011-04-051-2/+10
| | | | llvm-svn: 128913
* Make second source operand of LDRD pre/post explicit.Jim Grosbach2011-04-052-8/+28
| | | | | | Finish what r128736 started. llvm-svn: 128903
* Constants with multiple encodings (ARM):Johnny Chen2011-04-051-2/+3
| | | | | | | | | | An alternative syntax is available for a modified immediate constant that permits the programmer to specify the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where: <byte> is the numeric value of abcdefgh, in the range 0-255 <rot> is twice the numeric value of rotation, an even number in the range 0-30. llvm-svn: 128897
* Check for invalid register encodings for UMAAL and friends where:Johnny Chen2011-04-051-2/+49
| | | | | | | | | if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; if dHi == dLo then UNPREDICTABLE; rdar://problem/9230202 llvm-svn: 128895
* Convert ADCS and SBCS instructions into pseudos that are expanded to the ↵Owen Anderson2011-04-052-41/+56
| | | | | | ADC/ABC with the appropriate S-bit input value. llvm-svn: 128892
* Revamp the SjLj "dispatch setup" intrinsic.Bill Wendling2011-04-052-4/+4
| | | | | | | | | | | | It needed to be moved closer to the setjmp statement, because the code directly after the setjmp needs to know about values that are on the stack. Also, the 'bitcast' of the function context was causing a dead load. This wouldn't be too horrible, except that at -O0 it wasn't optimized out, and because it wasn't using the correct base pointer (if there is a VLA), it would try to access a value from a garbage address. <rdar://problem/9130540> llvm-svn: 128873
* Just use BL all the time. It's safer that way.Eric Christopher2011-04-051-9/+1
| | | | | | Fixes rdar://9184526 llvm-svn: 128869
* Fix SRS/SRSW encoding bits.Johnny Chen2011-04-051-0/+4
| | | | | | | | | rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with http://llvm.org/viewvc/llvm-project?view=rev&revision=128859. llvm-svn: 128864
* A8.6.105 MULJohnny Chen2011-04-041-1/+3
| | | | | | | | Inst{15-12} should be specified as 0b0000. rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL llvm-svn: 128862
* RFE encoding should also specify the "should be" encoding bits.Johnny Chen2011-04-043-28/+49
| | | | | | | | | rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while doing regression testings. llvm-svn: 128859
* Make OpcodeMask an unsigned long long literal to deal with overflow.Joerg Sonnenberger2011-04-041-1/+1
| | | | llvm-svn: 128847
* Fix incorrect alignment for NEON VST2b32_UPD.Johnny Chen2011-04-041-7/+132
| | | | | | rdar://problem/9225433 llvm-svn: 128841
* Insert code in the right location when lowering PowerPC atomics.Jakob Stoklund Olesen2011-04-041-2/+4
| | | | | | | This causes defs to dominate uses, no instructions after terminators, and other goodness. llvm-svn: 128836
* - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHTBruno Cardoso Lopes2011-04-047-32/+240
| | | | | | | | | | also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. llvm-svn: 128832
* Move transformation of JmpLink and related nodes done during instruction ↵Akira Hatanaka2011-04-042-59/+27
| | | | | | selection to Legalize phase. llvm-svn: 128830
* PowerPC atomic pseudos clobber CR0, they don't read it.Jakob Stoklund Olesen2011-04-042-2/+2
| | | | llvm-svn: 128829
* Use X0 instead of R0 for the zero register on ppc64.Jakob Stoklund Olesen2011-04-041-10/+13
| | | | | | The 32-bit R0 cannot be used where a 64-bit register is expected. llvm-svn: 128828
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-047-4/+81
| | | | llvm-svn: 128826
* Expand Op0Mask by one bit in preparation for the PadLock prefixes.Joerg Sonnenberger2011-04-043-50/+51
| | | | | | | | Define most shift masks incrementally to reduce the redundant hard-coding. Introduce new shift for the VEX flags to replace the magic constant 32 in various places. llvm-svn: 128822
* Remove some support for ReturnInsts with multiple operands, and forJay Foad2011-04-041-18/+0
| | | | | | | returning a scalar value in a function whose return type is a single- element structure or array. llvm-svn: 128810
* ptx: support setp's 4-operand formatChe-Liang Chiou2011-04-022-35/+86
| | | | llvm-svn: 128767
* Do some peephole optimizations to remove pointless VMOVs from Neon to integerCameron Zwarich2011-04-021-0/+31
| | | | | | | | registers that arise from argument shuffling with the soft float ABI. These instructions are particularly slow on Cortex A8. This fixes one half of <rdar://problem/8674845>. llvm-svn: 128759
* Fixed a bug in disassembly of STR_POST, where the immediate is the second ↵Johnny Chen2011-04-021-5/+13
| | | | | | | | | | operand in am2offset; instead of the second operand in addrmode_imm12. rdar://problem/9225289 llvm-svn: 128757
* Undo changes mistakenly made in revision 128750.Akira Hatanaka2011-04-022-27/+59
| | | | llvm-svn: 128751
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