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| author | Johnny Chen <johnny.chen@apple.com> | 2011-04-07 01:05:52 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-07 01:05:52 +0000 |
| commit | c0e86fb965d6944f030da4789f0fb816d8a42edb (patch) | |
| tree | d9b828435b16e0e485974f22115ffcabefe2d207 /llvm/lib/Target | |
| parent | 25c82240e98750c258cb7720fb6de51b1f122b88 (diff) | |
| download | bcm5719-llvm-c0e86fb965d6944f030da4789f0fb816d8a42edb.tar.gz bcm5719-llvm-c0e86fb965d6944f030da4789f0fb816d8a42edb.zip | |
The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
for USAD8 and USADA8.
rdar://problem/9247060
llvm-svn: 129047
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index fd4948552e2..48a748b8ca7 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -536,7 +536,7 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) { return false; case ARM::MLA: case ARM::MLS: case ARM::SMLABB: case ARM::SMLABT: case ARM::SMLATB: case ARM::SMLATT: case ARM::SMLAWB: case ARM::SMLAWT: - case ARM::SMMLA: case ARM::SMMLS: + case ARM::SMMLA: case ARM::SMMLS: case ARM::USADA8: if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15) return true; return false; @@ -545,6 +545,7 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) { case ARM::SMUAD: case ARM::SMUADX: // A8.6.167 SMLAD & A8.6.172 SMLSD case ARM::SMLAD: case ARM::SMLADX: case ARM::SMLSD: case ARM::SMLSDX: + case ARM::USAD8: if (R19_16 == 15 || R11_8 == 15 || R3_0 == 15) return true; return false; @@ -562,12 +563,13 @@ static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) { // Multiply Instructions. // MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS, -// SMLAD, SMLADX, SMLSD, SMLSDX: +// SMLAD, SMLADX, SMLSD, SMLSDX, USADA8 (for convenience): // Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12} // But note that register checking for {SMLAD, SMLADX, SMLSD, SMLSDX} is // only for {d, n, m}. // -// MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, SMUAD, SMUADX: +// MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, SMUAD, SMUADX, +// USAD8 (for convenience): // Rd{19-16} Rn{3-0} Rm{11-8} // // SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, |
