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| author | Johnny Chen <johnny.chen@apple.com> | 2011-04-05 23:28:00 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-05 23:28:00 +0000 |
| commit | f6e327c6a3fb587cfdcf6e2022896d7c0b909637 (patch) | |
| tree | 1c798302f53595bcec49637ada7116bbcba71798 /llvm/lib/Target | |
| parent | 78019ec14d77e2664ee40a3e15f3add5cc4fb882 (diff) | |
| download | bcm5719-llvm-f6e327c6a3fb587cfdcf6e2022896d7c0b909637.tar.gz bcm5719-llvm-f6e327c6a3fb587cfdcf6e2022896d7c0b909637.zip | |
Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register
encodings for DisassembleArithMiscFrm().
rdar://problem/9238659
llvm-svn: 128958
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 58f9c1f759c..8c89505a20f 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -1474,6 +1474,12 @@ static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID; + // Sanity check the registers, which should not be 15. + if (decodeRd(insn) == 15 || decodeRm(insn) == 15) + return false; + if (ThreeReg && decodeRn(insn) == 15) + return false; + MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, decodeRd(insn)))); ++OpIdx; @@ -1498,7 +1504,7 @@ static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, ARM_AM::ShiftOpc Opc = ARM_AM::no_shift; if (Opcode == ARM::PKHBT) Opc = ARM_AM::lsl; - else if (Opcode == ARM::PKHBT) + else if (Opcode == ARM::PKHTB) Opc = ARM_AM::asr; getImmShiftSE(Opc, ShiftAmt); MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShiftAmt))); |
