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* Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from ↵Craig Topper2011-09-131-0/+22
| | | | | | being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. llvm-svn: 139588
* Fix encoding of VMOVDQU to not simultaneously be 'TB OpSize' and 'XS'. 'XS' ↵Craig Topper2011-09-131-4/+4
| | | | | | is correct and seems to have been taking priority. llvm-svn: 139587
* Zap some junk from the ARM instruction descriptions.Eli Friedman2011-09-134-67/+0
| | | | llvm-svn: 139575
* Fix the assembler strings for a couple of atomic instructions. Doesn't ↵Eli Friedman2011-09-131-2/+2
| | | | | | really matter much in practice, but it's a bit cleaner. llvm-svn: 139563
* Tidy up a bit.Jim Grosbach2011-09-121-18/+9
| | | | llvm-svn: 139559
* Fix PR10845. SUBREG_TO_REG shouldn't be used when the input andBruno Cardoso Lopes2011-09-121-8/+8
| | | | | | destination types are equal! llvm-svn: 139553
* Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP ↵Owen Anderson2011-09-121-7/+88
| | | | | | either. llvm-svn: 139542
* Revert the wrong part of r139528, and fix testcases.Bruno Cardoso Lopes2011-09-121-4/+4
| | | | llvm-svn: 139541
* Fix encoding of PC-relative LDRSHW with an immediate offset.Owen Anderson2011-09-121-10/+19
| | | | llvm-svn: 139537
* There's no need to add additional predicate operands when converting a tB to ↵Owen Anderson2011-09-121-2/+0
| | | | | | a tBfar now. Fixes nightly test failures on armv6 Thumb. <rdar://problem/10110404> llvm-svn: 139531
* Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.Bruno Cardoso Lopes2011-09-121-9/+18
| | | | | | | | | | | | However with this fix it does now. Basically the operand order for the x86 target specific node is not the same as the instruction, but since the intrinsic need that specific order at the instruction definition, just change the order during legalization. Also, there were some wrong invertions of condition codes, such as GE => LE, GT => LT, fix that too. Fix PR10907. llvm-svn: 139528
* Organize a bit the operand names for CMPPS and CMPPDBruno Cardoso Lopes2011-09-121-18/+18
| | | | llvm-svn: 139527
* Realign BLEND patterns to match the general style for patterns in .td file.Bruno Cardoso Lopes2011-09-121-45/+42
| | | | llvm-svn: 139526
* Fix 80-columnsBruno Cardoso Lopes2011-09-121-12/+16
| | | | llvm-svn: 139525
* Port more encoding tests to decoding tests, and correct an improper Thumb2 ↵Owen Anderson2011-09-122-0/+36
| | | | | | pre-indexed load decoding this uncovered. llvm-svn: 139522
* Associate a MemOperand with LDWCP nodes introduced during ISel.Richard Osborne2011-09-121-3/+8
| | | | | | This information is required if we want LDWCP to be hoisted out of loops. llvm-svn: 139495
* Mark LDWCP as having no side effects.Richard Osborne2011-09-121-1/+1
| | | | llvm-svn: 139494
* Format patterns, remove unused X86blend patternsNadav Rotem2011-09-122-27/+34
| | | | llvm-svn: 139491
* Fix disassembling of one of the register/register forms of ↵Craig Topper2011-09-111-0/+62
| | | | | | MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. llvm-svn: 139486
* Fix disassembling of reverse register/register forms of ↵Craig Topper2011-09-111-4/+13
| | | | | | ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. llvm-svn: 139485
* CR fixes per Bruno's request.Nadav Rotem2011-09-113-94/+48
| | | | | | | Undo the changes from r139285 which added custom lowering to vselect. Add tablegen lowering for vselect. llvm-svn: 139479
* r139454 activates an assert in a case where we were doing the right thing ↵Eli Friedman2011-09-101-1/+9
| | | | | | anyway. Make that explicit, and un-XFAIL the testcase. llvm-svn: 139458
* Fix the asserts in lib/Target/X86/X86ELFWriterInfo.cpp andRichard Trieu2011-09-101-1/+1
| | | | | | | | | | | | lib/ExecutionEngine/MCJIT/MCJIT.cpp from: assert("error"); to: assert(0 && "error"); llvm-svn: 139456
* Fixed an assert from:Richard Trieu2011-09-101-1/+1
| | | | | | | | | | | | | | assert("not implemented for target shuffle node"); to: assert(0 && "not implemented for target shuffle node"); This causes a test failure in CodeGen/X86/palignr.ll which has been marked as XFAIL for the time being. Test failure filed at PR10901. llvm-svn: 139454
* Thumb2 parsing and encoding for MOV(immediate).Jim Grosbach2011-09-102-4/+58
| | | | | | | Some aliases for MOV(register) also to keep existing T1 tests happy when run in thumbv7 mode. llvm-svn: 139440
* LDM writeback is not allowed if Rn is in the target register list.Owen Anderson2011-09-091-0/+19
| | | | llvm-svn: 139432
* Fix an ambiguously nested if.Owen Anderson2011-09-091-2/+2
| | | | llvm-svn: 139431
* Fix buildbot breakage caused by r139415. I missed one instance of a ↵Owen Anderson2011-09-091-1/+5
| | | | | | manually create ARM::tB. llvm-svn: 139429
* Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.Owen Anderson2011-09-093-2/+27
| | | | llvm-svn: 139422
* O64 will not be supported.Akira Hatanaka2011-09-092-2/+1
| | | | llvm-svn: 139421
* Make F31 and D15 non-reserved registers.Akira Hatanaka2011-09-092-5/+1
| | | | llvm-svn: 139420
* Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson2011-09-099-23/+70
| | | | | | have a predicate operand, unlike conditional branches. llvm-svn: 139415
* Mips32 does not reserve even-numbered floating point registers.Akira Hatanaka2011-09-091-5/+0
| | | | llvm-svn: 139412
* Drop support for Mips1 and Mips2.Akira Hatanaka2011-09-099-87/+6
| | | | llvm-svn: 139405
* Implement vector-select support for avx256. Refactor the vblend ↵Nadav Rotem2011-09-094-30/+63
| | | | | | implementation to have tablegen match the instruction by the node type llvm-svn: 139400
* Thumb2 assembly parsing and encoding for MLA and MLS.Jim Grosbach2011-09-091-2/+2
| | | | llvm-svn: 139399
* Thumb2 assembly parsing and encoding for LDRSB.Jim Grosbach2011-09-091-1/+11
| | | | llvm-svn: 139389
* Drop support for Allegrex. Allegrex implements a variant of Mips2.Akira Hatanaka2011-09-092-23/+0
| | | | llvm-svn: 139383
* Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach2011-09-098-40/+125
| | | | llvm-svn: 139381
* Fix handling of Intel syntax disassembling of movs and stos to stop being ↵Craig Topper2011-09-091-12/+12
| | | | | | blank. Also fixed scas, and cmps to always print size suffix in Intel syntax since its abiguous without arguments. Fixes PR10875. llvm-svn: 139353
* Change default target architecture from Mips1 to Mips32r1 in preparation forAkira Hatanaka2011-09-092-2/+2
| | | | | | | | | removing support for Mips1 and Mips2. This change and the ones that follow have been discussed with and approved by Bruno. llvm-svn: 139344
* 80 columns.Akira Hatanaka2011-09-093-3/+3
| | | | llvm-svn: 139339
* All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.Owen Anderson2011-09-081-2/+3
| | | | llvm-svn: 139329
* Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.Owen Anderson2011-09-081-12/+21
| | | | llvm-svn: 139328
* Dix the 80-columns and remove unsupported v8i16 type from the list of legal ↵Nadav Rotem2011-09-081-9/+12
| | | | | | vselect types. llvm-svn: 139324
* Thumb2 assembly parsing and encoding for LDRD(immediate).Jim Grosbach2011-09-086-25/+226
| | | | | | Refactor operand handling for STRD as well. Tests for that forthcoming. llvm-svn: 139322
* Add a AVX version of a simple i64 -> f64 bitcast. This could beBruno Cardoso Lopes2011-09-081-7/+21
| | | | | | | triggered using llc with -O0, which wouldn't let it be folded and expose the lack of this pattern. llvm-svn: 139320
* * Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into aBruno Cardoso Lopes2011-09-082-643/+653
| | | | | | | | | | | | | | | | | | | | single field (Flags), which is a bitwise OR of items from the TB_* enum. This makes it easier to add new information in the future. * Gives every static array an equivalent layout: { RegOp, MemOp, Flags } * Adds a helper function, AddTableEntry, to avoid duplication of the insertion code. * Renames TB_NOT_REVERSABLE to TB_NO_REVERSE. * Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that it prevents addition of the Reg->Mem entry. (This is going to be used by Native Client, in the next CL). Patch by David Meyer llvm-svn: 139311
* Add AVX versions of blend vector operations and fix some issues noticedBruno Cardoso Lopes2011-09-083-15/+22
| | | | | | | | | | | | in Nadav's r139285 and r139287 commits. 1) Rename vsel.ll to a more descriptive name 2) Change the order of BLEND operands to "Op1, Op2, Cond", this is necessary because PBLENDVB is already used in different places with this order, and it was being emitted in the wrong way for vselect 3) Add AVX patterns and tests for the same SSE41 instructions llvm-svn: 139305
* Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.Bruno Cardoso Lopes2011-09-081-4/+14
| | | | | | | Triggered using llc -O0. Also fix some SET0PS patterns to their AVX forms and test it on the testcase. llvm-svn: 139304
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