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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-09-12 22:59:23 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-09-12 22:59:23 +0000 |
| commit | ff8d8a830e1f71d5b635804e1ac32c56c51e0953 (patch) | |
| tree | da2a84be9010dde6fcc9fbe90f7e04a477f50ae9 /llvm/lib/Target | |
| parent | a8315c3f2b877c5640883159333d43a754ac4cbe (diff) | |
| download | bcm5719-llvm-ff8d8a830e1f71d5b635804e1ac32c56c51e0953.tar.gz bcm5719-llvm-ff8d8a830e1f71d5b635804e1ac32c56c51e0953.zip | |
Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and
destination types are equal!
llvm-svn: 139553
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 0d86902e01d..63d97980a4f 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -4250,11 +4250,11 @@ let Predicates = [HasAVX] in { // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part. let AddedComplexity = 20 in { def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))), - (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrm addr:$src), sub_xmm)>; + (VMOVZDI2PDIrm addr:$src)>; def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))), - (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrm addr:$src), sub_xmm)>; + (VMOVZDI2PDIrm addr:$src)>; def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))), - (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrm addr:$src), sub_xmm)>; + (VMOVZDI2PDIrm addr:$src)>; } // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext. def : Pat<(v8i32 (X86vzmovl (insert_subvector undef, @@ -4347,11 +4347,11 @@ let Predicates = [HasSSE2], AddedComplexity = 20 in { let Predicates = [HasAVX], AddedComplexity = 20 in { def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))), - (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>; + (VMOVZQI2PQIrm addr:$src)>; def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))), - (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>; + (VMOVZQI2PQIrm addr:$src)>; def : Pat<(v2i64 (X86vzload addr:$src)), - (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>; + (VMOVZQI2PQIrm addr:$src)>; } //===---------------------------------------------------------------------===// @@ -4392,9 +4392,9 @@ let AddedComplexity = 20 in { } let Predicates = [HasAVX] in { def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))), - (SUBREG_TO_REG (i64 0), (VMOVZPQILo2PQIrm addr:$src), sub_xmm)>; + (VMOVZPQILo2PQIrm addr:$src)>; def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))), - (SUBREG_TO_REG (i64 0), (MOVZPQILo2PQIrr VR128:$src), sub_xmm)>; + (VMOVZPQILo2PQIrr VR128:$src)>; } } |
