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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-09-08 18:05:02 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-09-08 18:05:02 +0000 |
| commit | ea8d803bb088a35f84cb29e2b827776178214356 (patch) | |
| tree | 9773e4349fefb4413d5cab8b1e7121aab82f0799 /llvm/lib/Target | |
| parent | 6a40b088e902faa7c474966758104347a3928ace (diff) | |
| download | bcm5719-llvm-ea8d803bb088a35f84cb29e2b827776178214356.tar.gz bcm5719-llvm-ea8d803bb088a35f84cb29e2b827776178214356.zip | |
Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.
Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.
llvm-svn: 139304
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index c210a987dc5..9148c76ce0c 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -536,15 +536,15 @@ let Predicates = [HasAVX] in { // Move scalar to XMM zero-extended, zeroing a VR128 then do a // MOVS{S,D} to the lower bits. def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))), - (VMOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>; + (VMOVSSrr (v4f32 (AVX_SET0PS)), FR32:$src)>; def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))), - (VMOVSSrr (v4f32 (V_SET0PS)), + (VMOVSSrr (v4f32 (AVX_SET0PS)), (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>; def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))), - (VMOVSSrr (v4i32 (V_SET0PI)), + (VMOVSSrr (v4i32 (AVX_SET0PI)), (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>; def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))), - (VMOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>; + (VMOVSDrr (v2f64 (AVX_SET0PS)), FR64:$src)>; } let AddedComplexity = 20 in { @@ -579,6 +579,16 @@ let Predicates = [HasAVX] in { (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))), (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>; } + def : Pat<(v8f32 (X86vzmovl (insert_subvector undef, + (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))), + (SUBREG_TO_REG (i32 0), + (v4f32 (VMOVSSrr (v4f32 (AVX_SET0PS)), FR32:$src)), + sub_xmm)>; + def : Pat<(v4f64 (X86vzmovl (insert_subvector undef, + (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))), + (SUBREG_TO_REG (i64 0), + (v2f64 (VMOVSDrr (v2f64 (AVX_SET0PS)), FR64:$src)), + sub_xmm)>; // Extract and store. def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), |
