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* Initialize X86 DataLayout based on the Triple only.Eric Christopher2014-08-091-2/+3
| | | | llvm-svn: 215279
* Temporarily Revert "Nuke the old JIT." as it's not quite ready toEric Christopher2014-08-071-0/+3
| | | | | | | | | | | be deleted. This will be reapplied as soon as possible and before the 3.6 branch date at any rate. Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reverts commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 215154
* Nuke the old JIT.Rafael Espindola2014-08-071-3/+0
| | | | | | | | | I am sure we will be finding bits and pieces of dead code for years to come, but this is a good start. Thanks to Lang Hames for making MCJIT a good replacement! llvm-svn: 215111
* [x32] Use ebp/esp as frame and stack pointerPavel Chupin2014-08-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | Summary: Since pointers are 32-bit on x32 we can use ebp and esp as frame and stack pointer. Some operations like PUSH/POP and CFI_INSTRUCTION still require 64-bit register, so using 64-bit MachineFramePtr where required. X86_64 NaCl uses 64-bit frame/stack pointers, however it's been found that both isTarget64BitLP64 and isTarget64BitILP32 are true for NaCl. Addressing this issue here as well by making isTarget64BitLP64 false. Also mark hasReservedSpillSlot unreachable on X86. See inlined comments. Test Plan: Add one new simple test and upgrade 2 existing with x32 target case. Reviewers: nadav, dschuff Subscribers: llvm-commits, zinovy.nis Differential Revision: http://reviews.llvm.org/D4617 llvm-svn: 215091
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-7/+18
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Add support for the X86 secure guard extensions instructions in assembler (SGX).Kevin Enderby2014-07-311-0/+4
| | | | | | | | | | | | | This allows assembling the two new instructions, encls and enclu for the SKX processor model. Note the diffs are a bigger than what might think, but to fit the new MRM_CF and MRM_D7 in things in the right places things had to be renumbered and shuffled down causing a bit more diffs. rdar://16228228 llvm-svn: 214460
* [SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features.Robert Khasanov2014-07-211-3/+15
| | | | | | | | | | | | Enabling HasAVX512{DQ,BW,VL} predicates. Adding VK2, VK4, VK32, VK64 masked register classes. Adding new types (v64i8, v32i16) to VR512. Extending calling conventions for new types (v64i8, v32i16) Patch by Zinovy Nis <zinovy.y.nis@intel.com> Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 213545
* Move Post RA Scheduling flag bit into SchedMachineModelSanjay Patel2014-07-151-10/+4
| | | | | | | | | | | | | | | | | | | | | Refactoring; no functional changes intended Removed PostRAScheduler bits from subtargets (X86, ARM). Added PostRAScheduler bit to MCSchedModel class. This bit is set by a CPU's scheduling model (if it exists). Removed enablePostRAScheduler() function from TargetSubtargetInfo and subclasses. Fixed the existing enablePostMachineScheduler() method to use the MCSchedModel (was just returning false!). Added methods to TargetSubtargetInfo to allow overrides for AntiDepBreakMode, CriticalPathRCs, and OptLevel for PostRAScheduling. Added enablePostRAScheduler() function to PostRAScheduler class which queries the subtarget for the above values. Preserved existing scheduler behavior for ARM, MIPS, PPC, and X86: a. ARM overrides the CPU's postRA settings by enabling postRA for any non-Thumb or Thumb2 subtarget. b. MIPS overrides the CPU's postRA settings by enabling postRA for everything. c. PPC overrides the CPU's postRA settings by enabling postRA for everything. d. X86 is the only target that actually has postRA specified via sched model info. Differential Revision: http://reviews.llvm.org/D4217 llvm-svn: 213101
* Move to a private function to initialize the subtarget dependenciesEric Christopher2014-06-111-10/+13
| | | | | | so that we can use initializer lists for the X86Subtarget. llvm-svn: 210614
* Use unique_ptr for X86Subtarget pointer members.Eric Christopher2014-06-101-9/+10
| | | | llvm-svn: 210606
* Move all of the x86 subtarget initialized variables down into the x86 subtargetEric Christopher2014-06-091-1/+23
| | | | | | from the x86 target machine. Should be no functional change. llvm-svn: 210479
* [X86] Use ADD/SUB instead of INC/DEC for SilvermontAlexey Volkov2014-06-091-0/+4
| | | | | | | | | | | | According to Intel Software Optimization Manual on Silvermont INC or DEC instructions require an additional uop to merge the flags. As a result, a branch instruction depending on an INC or a DEC instruction incurs a 1 cycle penalty. Differential Revision: http://reviews.llvm.org/D3990 llvm-svn: 210466
* Make early if conversion dependent upon the subtarget and addEric Christopher2014-05-211-0/+2
| | | | | | | a subtarget hook to enable. Unconditionally add to the pass pipeline for targets that might want to use it. No functional change. llvm-svn: 209340
* [X86] Tune LEA usage for SilvermontAlexey Volkov2014-05-201-0/+5
| | | | | | | | | | | | | According to Intel Software Optimization Manual on Silvermont in some cases LEA is better to be replaced with ADD instructions: "The rule of thumb for ADDs and LEAs is that it is justified to use LEA with a valid index and/or displacement for non-destructive destination purposes (especially useful for stack offset cases), or to use a SCALE. Otherwise, ADD(s) are preferable." Differential Revision: http://reviews.llvm.org/D3826 llvm-svn: 209198
* X86: Remove TargetMachine CPU auto-detection.Jim Grosbach2014-04-121-4/+0
| | | | | | | | This logic is properly in the realm of whatever is creating the TargetMachine. This makes plain 'llc foo.ll' consistent across heterogenous machines. llvm-svn: 206094
* Added isTargetWindowsMSVC(), renamed isTargetMingw() to isTargetWindowsGNU()Yaron Keren2014-04-021-2/+12
| | | | | | | | | and isTargetCygwin() to isTargetWindowsCygwin() to be consistent with the four Windows environments in Triple.h. Suggestion by Saleem Abdulrasool! llvm-svn: 205393
* isTargetWindows() renamed to isTargetKnownWindowsMSVC()Yaron Keren2014-04-011-2/+2
| | | | | | | | to reflect its current functionality. Based on Takumi NAKAMURA suggestion. llvm-svn: 205338
* [C++11] Mark more classes in the X86 target as 'final'.Craig Topper2014-03-311-1/+1
| | | | llvm-svn: 205166
* X86Subtarget.h: isTargetWindows() should tell whether he is targeting msvc.NAKAMURA Takumi2014-03-301-2/+1
| | | | | | | FYI, !isWindowsGNUEnvironment() is insufficient. It missed cygwin. FIXME: The name "isTargetWindows" should be fixed. llvm-svn: 205124
* Canonicalise Windows target triple spellingsSaleem Abdulrasool2014-03-271-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Construct a uniform Windows target triple nomenclature which is congruent to the Linux counterpart. The old triples are normalised to the new canonical form. This cleans up the long-standing issue of odd naming for various Windows environments. There are four different environments on Windows: MSVC: The MS ABI, MSVCRT environment as defined by Microsoft GNU: The MinGW32/MinGW32-W64 environment which uses MSVCRT and auxiliary libraries Itanium: The MSVCRT environment + libc++ built with Itanium ABI Cygnus: The Cygwin environment which uses custom libraries for everything The following spellings are now written as: i686-pc-win32 => i686-pc-windows-msvc i686-pc-mingw32 => i686-pc-windows-gnu i686-pc-cygwin => i686-pc-windows-cygnus This should be sufficiently flexible to allow us to target other windows environments in the future as necessary. llvm-svn: 204977
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-091-2/+2
| | | | | | class. llvm-svn: 203378
* Switch all uses of LLVM_OVERRIDE to just use 'override' directly.Craig Topper2014-03-021-1/+1
| | | | llvm-svn: 202621
* [x86] Kill gratuitous X86_{32,64}TargetMachine subclasses, use X86TargetMachineDavid Woodhouse2014-01-081-1/+1
| | | | llvm-svn: 198720
* [x86] Add basic support for .code16Craig Topper2014-01-061-1/+15
| | | | | | | | | | | This is not really expected to work right yet. Mostly because we will still emit the OpSize (0x66) prefix in all the wrong places, along with a number of other corner cases. Those will all be fixed in the subsequent commits. Patch from David Woodhouse. llvm-svn: 198584
* Synchronize the NaCl DataLayout strings with the ones in clang.Rafael Espindola2013-12-191-1/+2
| | | | | | Patch by Derek Schuff. llvm-svn: 197640
* Make Triple's isOSBinFormatXXX functions partition triple-space.Tim Northover2013-12-101-9/+5
| | | | | | | | | | | Most users would be surprised if "isCOFF" and "isMachO" were simultaneously true, unless they'd put the compiler in a box with a gun attached to a photon detector. This makes sure precisely one of the three formats is true for any triple and simplifies some target logic based on that. llvm-svn: 196934
* SHLD/SHRD are VectorPath (microcode) instructions known to have poor latency ↵Ekaterina Romanova2013-11-211-0/+4
| | | | | | | | | | on certain architectures. While generating SHLD/SHRD instructions is acceptable when optimizing for size, optimizing for speed on these platforms should be implemented using alternative sequences of instructions composed of add, adc, shr, shl, or and lea which are directPath instructions. These alternative instructions not only have a lower latency but they also increase the decode bandwidth by allowing simultaneous decoding of a third directPath instruction. AMD's processors family K7, K8, K10, K12, K15 and K16 are known to have SHLD/SHRD instructions with very poor latency. Optimization guides for these processors recommend using an alternative sequence of instructions. For these AMD's processors, I disabled folding (or (x << c) | (y >> (64 - c))) when we are not optimizing for size. It might be beneficial to disable this folding for some of the Intel's processors. However, since I couldn't find specific recommendations regarding using SHLD/SHRD instructions on Intel's processors, I haven't disabled this peephole for Intel. llvm-svn: 195383
* (this is a corrected patch)Yaron Keren2013-10-231-0/+2
| | | | | | | | | | | | | | Calling _chkstk is required on ELF as well as COFF on Windows. Without _chkstk, functions requiring large stack crash in initialization code. Previous code tested for COFF format but not Mach-O and this patch modifies the code to test for Windows OS (both Windows target and MingW target) but not Mach-O object format: Looks like macho environment was used to build some EFI code. Credits to Andrew MacPherson. llvm-svn: 193289
* Revert "Calling _chkstk is required on ELF as well as COFF on Windows. ↵Rafael Espindola2013-10-231-2/+0
| | | | | | | | | | Without _chkstk functions requiring large stack crash in initialization code. Previous code tested for COFF format but not Mach-O and this patch modifies the code to test for Windows." This reverts commit r193263. It is causing CodeGen/X86/mingw-alloca.ll to fail. llvm-svn: 193275
* Calling _chkstk is required on ELF as well as COFF on Windows. Yaron Keren2013-10-231-0/+2
| | | | | | | | | | Without _chkstk functions requiring large stack crash in initialization code. Previous code tested for COFF format but not Mach-O and this patch modifies the code to test for Windows. Credits to Andrew MacPherson. llvm-svn: 193263
* Enable MI Sched for x86.Andrew Trick2013-10-151-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
* Adding a feature flag to the llvm backend for x86 TBM instruction set.Yunzhong Gao2013-09-241-0/+4
| | | | | | | | | | Adding TBM feature to bdver2 processor; piledriver supports this instruction set according to the following document: http://developer.amd.com/wordpress/media/2012/10/New-Bulldozer-and-Piledriver-Instructions.pdf Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1692 llvm-svn: 191324
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-131-1/+1
| | | | | | | | | | | Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. llvm-svn: 190717
* Partial support for Intel SHA Extensions (sha1rnds4)Ben Langmuir2013-09-121-0/+4
| | | | | | | | | Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. llvm-svn: 190611
* Clean up some usage of Triple. The base class has methods for determining ↵Cameron Esfahani2013-08-291-4/+2
| | | | | | if the target is iOS and Linux. llvm-svn: 189604
* X86Subtarget.h: Recognize x86_64-cygwin.NAKAMURA Takumi2013-08-281-4/+1
| | | | | | In the LLVM side, x86_64-cygwin is almost as same as x86_64-mingw32. llvm-svn: 189436
* Rename mattr names for AVX-512 to from avx-512 -> avx512f, avx-512-pfi -> ↵Craig Topper2013-08-211-2/+2
| | | | | | av512pf, avx-512-cdi -> avx512cd, avx-512-eri->avx512er. This matches better with official docs and what gcc patches appearto be using. I didn't touch the has* functions or the feature flag names to avoid change the td and lowering file while commits are still happening. llvm-svn: 188859
* I'm starting to commit KNL backend. I'll push patches one-by-one. This patch ↵Elena Demikhovsky2013-07-241-1/+14
| | | | | | | | includes support for the extended register set XMM16-31, YMM16-31, ZMM0-31. The full ISA you can see here: http://software.intel.com/en-us/intel-isa-extensions llvm-svn: 187030
* Target/X86: Add explicit Win64 and System V/x86-64 calling conventions.Charles Davis2013-07-121-1/+7
| | | | | | | | | | | | | | | Summary: This patch adds explicit calling convention types for the Win64 and System V/x86-64 ABIs. This allows code to override the default, and use the Win64 convention on a target that wants to use SysV (and vice-versa). This is needed to implement the `ms_abi` and `sysv_abi` GNU attributes. Reviewers: CC: llvm-svn: 186144
* Revert "Temporarily enable MI-Sched on X86."Andrew Trick2013-06-251-4/+1
| | | | | | This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c. llvm-svn: 184823
* Temporarily enable MI-Sched on X86.Andrew Trick2013-06-241-1/+4
| | | | | | | Sorry for the unit test churn. I'll try to make the change permanently next time. llvm-svn: 184705
* This patch adds the X86FixupLEAs pass, which will reduce instructionPreston Gurd2013-04-251-0/+4
| | | | | | | | latency for certain models of the Intel Atom family, by converting instructions into their equivalent LEA instructions, when it is both useful and possible to do so. llvm-svn: 180573
* Add support of RDSEED defined in AVX2 extensionMichael Liao2013-03-281-0/+4
| | | | llvm-svn: 178314
* For the current Atom processor, the fastest way to handle a callPreston Gurd2013-03-271-0/+5
| | | | | | | | | | | | | indirect through a memory address is to load the memory address into a register and then call indirect through the register. This patch implements this improvement by modifying SelectionDAG to force a function address which is a memory reference to be loaded into a virtual register. Patch by Sriram Murali. llvm-svn: 178171
* Add HLE target featureMichael Liao2013-03-261-0/+4
| | | | llvm-svn: 178082
* Add PREFETCHW codegen supportMichael Liao2013-03-261-0/+4
| | | | | | - Add 'PRFCHW' feature defined in AVX2 ISA extension llvm-svn: 178040
* Reinitialize the ivars in the subtarget so that they can be reset with the ↵Bill Wendling2013-02-161-1/+3
| | | | | | new features. llvm-svn: 175336
* Temporary revert of 175320.Bill Wendling2013-02-151-3/+1
| | | | llvm-svn: 175322
* Reinitialize the ivars in the subtarget.Bill Wendling2013-02-151-1/+3
| | | | | | | When we're recalculating the feature set of the subtarget, we need to have the ivars in their initial state. llvm-svn: 175320
* Use the 'target-features' and 'target-cpu' attributes to reset the subtarget ↵Bill Wendling2013-02-151-1/+7
| | | | | | | | | | features. If two functions require different features (e.g., `-mno-sse' vs. `-msse') then we want to honor that, especially during LTO. We can do that by resetting the subtarget's features depending upon the 'target-feature' attribute. llvm-svn: 175314
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