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authorElena Demikhovsky <elena.demikhovsky@intel.com>2013-07-24 11:02:47 +0000
committerElena Demikhovsky <elena.demikhovsky@intel.com>2013-07-24 11:02:47 +0000
commit8cfb43f73b23715c6acc14b13178c3f9a4b9edab (patch)
tree91d4752cebb48a273c265cdf151d4d6127d5e3a9 /llvm/lib/Target/X86/X86Subtarget.h
parent83ea195d40f2017f94bd88c3efef84c9529fa640 (diff)
downloadbcm5719-llvm-8cfb43f73b23715c6acc14b13178c3f9a4b9edab.tar.gz
bcm5719-llvm-8cfb43f73b23715c6acc14b13178c3f9a4b9edab.zip
I'm starting to commit KNL backend. I'll push patches one-by-one. This patch includes support for the extended register set XMM16-31, YMM16-31, ZMM0-31.
The full ISA you can see here: http://software.intel.com/en-us/intel-isa-extensions llvm-svn: 187030
Diffstat (limited to 'llvm/lib/Target/X86/X86Subtarget.h')
-rw-r--r--llvm/lib/Target/X86/X86Subtarget.h15
1 files changed, 14 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h
index 01a28d0fd1d..87932388703 100644
--- a/llvm/lib/Target/X86/X86Subtarget.h
+++ b/llvm/lib/Target/X86/X86Subtarget.h
@@ -42,7 +42,7 @@ enum Style {
class X86Subtarget : public X86GenSubtargetInfo {
protected:
enum X86SSEEnum {
- NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
+ NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512
};
enum X863DNowEnum {
@@ -169,6 +169,15 @@ protected:
/// address generation (AG) time.
bool LEAUsesAG;
+ /// Processor has AVX-512 PreFetch Instructions
+ bool HasPFI;
+
+ /// Processor has AVX-512 Exponential and Reciprocal Instructions
+ bool HasERI;
+
+ /// Processor has AVX-512 Conflict Detection Instructions
+ bool HasCDI;
+
/// stackAlignment - The minimum alignment known to hold of the stack frame on
/// entry to the function and which must be maintained by every function.
unsigned stackAlignment;
@@ -249,6 +258,7 @@ public:
bool hasSSE42() const { return X86SSELevel >= SSE42; }
bool hasAVX() const { return X86SSELevel >= AVX; }
bool hasAVX2() const { return X86SSELevel >= AVX2; }
+ bool hasAVX512() const { return X86SSELevel >= AVX512; }
bool hasFp256() const { return hasAVX(); }
bool hasInt256() const { return hasAVX2(); }
bool hasSSE4A() const { return HasSSE4A; }
@@ -282,6 +292,9 @@ public:
bool padShortFunctions() const { return PadShortFunctions; }
bool callRegIndirect() const { return CallRegIndirect; }
bool LEAusesAG() const { return LEAUsesAG; }
+ bool hasCDI() const { return HasCDI; }
+ bool hasPFI() const { return HasPFI; }
+ bool hasERI() const { return HasERI; }
bool isAtom() const { return X86ProcFamily == IntelAtom; }
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