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| author | Michael Liao <michael.liao@intel.com> | 2013-03-26 17:47:11 +0000 |
|---|---|---|
| committer | Michael Liao <michael.liao@intel.com> | 2013-03-26 17:47:11 +0000 |
| commit | 5173ee03af6cbfac8420bd49fad8ed85c2a34763 (patch) | |
| tree | 798a8351ba1a1df99a86e2240537c41f45f4f12c /llvm/lib/Target/X86/X86Subtarget.h | |
| parent | bce7c77d852d85ba7fab3bfb60e8bdecdd01763a (diff) | |
| download | bcm5719-llvm-5173ee03af6cbfac8420bd49fad8ed85c2a34763.tar.gz bcm5719-llvm-5173ee03af6cbfac8420bd49fad8ed85c2a34763.zip | |
Add PREFETCHW codegen support
- Add 'PRFCHW' feature defined in AVX2 ISA extension
llvm-svn: 178040
Diffstat (limited to 'llvm/lib/Target/X86/X86Subtarget.h')
| -rw-r--r-- | llvm/lib/Target/X86/X86Subtarget.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h index e97da4b6f4f..b9f29fdcee0 100644 --- a/llvm/lib/Target/X86/X86Subtarget.h +++ b/llvm/lib/Target/X86/X86Subtarget.h @@ -124,6 +124,9 @@ protected: /// HasADX - Processor has ADX instructions. bool HasADX; + /// HasPRFCHW - Processor has PRFCHW instructions. + bool HasPRFCHW; + /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow. bool IsBTMemSlow; @@ -254,6 +257,7 @@ public: bool hasBMI2() const { return HasBMI2; } bool hasRTM() const { return HasRTM; } bool hasADX() const { return HasADX; } + bool hasPRFCHW() const { return HasPRFCHW; } bool isBTMemSlow() const { return IsBTMemSlow; } bool isUnalignedMemAccessFast() const { return IsUAMemFast; } bool hasVectorUAMem() const { return HasVectorUAMem; } |
