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* Rename instructions for consistency sake.Evan Cheng2006-05-311-10/+20
| | | | llvm-svn: 28594
* getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.Evan Cheng2006-05-181-0/+16
| | | | llvm-svn: 28378
* X86 integer register classes naming changes. Make them consistent with FP, ↵Evan Cheng2006-05-161-15/+15
| | | | | | vector classes. llvm-svn: 28324
* More coverity fixesChris Lattner2006-05-121-1/+0
| | | | llvm-svn: 28266
* Fixing truncate. Previously we were emitting truncate from r16 to r8 asEvan Cheng2006-05-081-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | movw. That is we promote the destination operand to r16. So %CH = TRUNC_R16_R8 %BP is emitted as movw %bp, %cx. This is incorrect. If %cl is live, it would be clobbered. Ideally we want to do the opposite, that is emitted it as movb ??, %ch But this is not possible since %bp does not have a r8 sub-register. We are now defining a new register class R16_ which is a subclass of R16 containing only those 16-bit registers that have r8 sub-registers (i.e. AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the value to the R16_ class, followed by a TRUNC_R16_R8. Due to bug 770, the register colaescer is not going to coalesce between R16 and R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it can only be eliminated if we are lucky that source and destination registers are the same. llvm-svn: 28164
* Better implementation of truncate. ISel matches it to a pseudo instructionEvan Cheng2006-05-051-0/+76
| | | | | | | | that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And if the destination gets allocated a subregister of the source operand, then the instruction will not be emitted at all. llvm-svn: 28119
* Remove and simplify some more machineinstr/machineoperand stuff.Chris Lattner2006-05-041-9/+9
| | | | llvm-svn: 28105
* Move some methods out of MachineInstr into MachineOperandChris Lattner2006-05-041-2/+2
| | | | llvm-svn: 28102
* There shalt be only one "immediate" operand type!Chris Lattner2006-05-041-1/+1
| | | | llvm-svn: 28099
* Remove a bunch more SparcV9 specific stuffChris Lattner2006-05-041-1/+1
| | | | llvm-svn: 28093
* Use movaps instead of movapd for spill / restore.Evan Cheng2006-04-281-2/+2
| | | | llvm-svn: 28005
* MakeMIInst() should handle jump table index operands.Evan Cheng2006-04-241-0/+3
| | | | llvm-svn: 27955
* - PEXTRW cannot take a memory location as its first source operand.Evan Cheng2006-04-181-2/+1
| | | | | | - PINSRWrmi encoding bug. llvm-svn: 27818
* SHUFP{S|D}, PSHUF* encoding bugs. Left out the mask immediate operand.Evan Cheng2006-04-181-5/+5
| | | | llvm-svn: 27817
* Encoding bug: CMPPSrmi, CMPPDrmi dropped operand 2 (condtion immediate).Evan Cheng2006-04-181-2/+2
| | | | llvm-svn: 27815
* Incorrect foldMemoryOperand entriesEvan Cheng2006-04-171-12/+6
| | | | llvm-svn: 27763
* Can't fold loads into alias vector SSE ops used for scalar operation. The loadEvan Cheng2006-04-161-8/+0
| | | | | | | address has to be 16-byte aligned but the values aren't spilled to 128-bit locations. llvm-svn: 27732
* Added SSE (and other) entries to foldMemoryOperand().Evan Cheng2006-04-141-19/+155
| | | | llvm-svn: 27716
* We were not adjusting the frame size to ensure proper alignment when alloca /Evan Cheng2006-04-141-30/+23
| | | | | | | | vla are present in the function. This causes a crash when a leaf function allocates space on the stack used to store / load with 128-bit SSE instructions. llvm-svn: 27698
* Use movaps to do VR128 reg-to-reg copies for now. It's shorter and available ↵Evan Cheng2006-04-101-1/+1
| | | | | | for SSE1. llvm-svn: 27554
* Foundation for call frame information.Jim Laskey2006-04-071-1/+5
| | | | llvm-svn: 27491
* Minor fixes + naming changes.Evan Cheng2006-04-041-2/+2
| | | | llvm-svn: 27410
* Expose base register for DwarfWriter. Refactor code accordingly.Jim Laskey2006-03-281-9/+2
| | | | llvm-svn: 27225
* Translate llvm target registers to dwarf register numbers properly.Jim Laskey2006-03-271-1/+1
| | | | llvm-svn: 27180
* Add support to locate local variables in frames (early version.)Jim Laskey2006-03-231-0/+12
| | | | llvm-svn: 26994
* Use the generic vector register classes VR64 / VR128 rather than V4F32,Evan Cheng2006-03-181-9/+3
| | | | | | V8I16, etc. llvm-svn: 26838
* Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi.Evan Cheng2006-03-171-0/+9
| | | | llvm-svn: 26817
* Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g.Evan Cheng2006-03-171-6/+18
| | | | | | ADD32ri8. llvm-svn: 26816
* Fix an obvious bug exposed when we are doingEvan Cheng2006-02-251-1/+2
| | | | | | | | ADD X, 4 ==> MOV32ri $X+4, ... llvm-svn: 26366
* Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64.Evan Cheng2006-02-211-2/+6
| | | | | | Added generic vector types: VR64 and VR128. llvm-svn: 26295
* Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bitEvan Cheng2006-02-201-6/+6
| | | | | | packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32). llvm-svn: 26294
* 1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. ThisEvan Cheng2006-02-161-2/+8
| | | | | | | | | | | proves to be worth 20% on Ptrdist/ks. Might be related to dependency breaking support. 2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These are used for FR32 / FR64 reg-to-reg copies. 3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to spill / restore FsMOVAPSrr and FsMOVAPDrr. llvm-svn: 26241
* Use movaps / movapd to spill / restore V4F4 / V2F8 registers.Evan Cheng2006-02-161-4/+12
| | | | llvm-svn: 26240
* Use movaps / movapd (instead of movss / movsd) to do FR32 / FR64 reg to regEvan Cheng2006-02-161-2/+2
| | | | | | | | | | | | | | | | | transfer. According to the Intel P4 Optimization Manual: Moves that write a portion of a register can introduce unwanted dependences. The movsd reg, reg instruction writes only the bottom 64 bits of a register, not to all 128 bits. This introduces a dependence on the preceding instruction that produces the upper 64 bits (even if those bits are not longer wanted). The dependence inhibits register renaming, and thereby reduces parallelism. Not to mention movaps is shorter than movss. llvm-svn: 26226
* When rewriting frame instructions, emit the appropriate small-immediateChris Lattner2006-02-031-13/+21
| | | | | | instruction when possible. llvm-svn: 25938
* Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far ↵Chris Lattner2006-02-021-46/+0
| | | | | | more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
* implement isStoreToStackSlotChris Lattner2006-02-021-0/+23
| | | | llvm-svn: 25911
* Added SSE entries to foldMemoryOperand().Evan Cheng2006-02-011-1/+49
| | | | llvm-svn: 25888
* Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS.Evan Cheng2006-01-091-2/+0
| | | | llvm-svn: 25158
* * Fast call support.Evan Cheng2006-01-061-1/+2
| | | | | | * FP cmp, setcc, etc. llvm-svn: 25117
* Let the helper functions know about X86::FR32RegClass and X86::FR64RegClass.Evan Cheng2005-12-241-6/+6
| | | | llvm-svn: 25004
* * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.Evan Cheng2005-12-231-0/+1
| | | | | | | | * Added a pseudo instruction (for each target) that represent "return void". This is a workaround for lack of optional flag operand (return void is not lowered so it does not have a flag operand.) llvm-svn: 24997
* Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patternsChris Lattner2005-12-211-4/+3
| | | | | | | | | | | | | | | that were overloaded to work before and after the stackifier runs. With the new clean world, it is possible to write patterns for these instructions: woo! This also adds a few simple patterns here and there, though there are a lot still missing. These should be easy to add though. :) See the comments under "Floating Point Stack Support" for more details on the new world order. This patch as absolutely no effect on the generated code, woo! llvm-svn: 24899
* Properly split f32 and f64 into separate register classes for scalar sse fpNate Begeman2005-10-141-5/+11
| | | | | | fixing a bunch of nasty hackery llvm-svn: 23735
* simplify this code using the new regclass info passed inChris Lattner2005-09-301-29/+45
| | | | llvm-svn: 23557
* Pass extra regclasses into spilling codeChris Lattner2005-09-301-2/+4
| | | | llvm-svn: 23537
* Implement the isLoadFromStackSlot interfaceChris Lattner2005-09-191-0/+25
| | | | llvm-svn: 23387
* The simple isel being gone makes this dead!Chris Lattner2005-08-191-19/+0
| | | | llvm-svn: 22914
* Eliminate all remaining tabs and trailing spaces.Jeff Cohen2005-07-271-4/+4
| | | | llvm-svn: 22523
* First round of support for doing scalar FP using the SSE2 ISA extension andNate Begeman2005-07-061-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XMM registers. There are many known deficiencies and fixmes, which will be addressed ASAP. The major benefit of this work is that it will allow the LLVM register allocator to allocate FP registers across basic blocks. The x86 backend will still default to x87 style FP. To enable this work, you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc. An example before and after would be for: double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i) Sum += P[i]; return Sum; } The inner loop looks like the following: x87: .LBB_foo_1: # no_exit fldl (%esp) faddl (%eax,%ecx,8) fstpl (%esp) incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit SSE2: addsd (%eax,%ecx,8), %xmm0 incl %ecx cmpl $1000, %ecx #FP_REG_KILL jne .LBB_foo_1 # no_exit llvm-svn: 22340
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