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| author | Chris Lattner <sabre@nondot.org> | 2005-12-21 07:47:04 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-12-21 07:47:04 +0000 |
| commit | f431ad4477efef96da82f6ce8cd2d990521891a8 (patch) | |
| tree | d89dd8ec563843e9b463ac98c9a6ade0fc0b27d5 /llvm/lib/Target/X86/X86RegisterInfo.cpp | |
| parent | 988827a4824b48c34b76ef2f7806333f6b674da9 (diff) | |
| download | bcm5719-llvm-f431ad4477efef96da82f6ce8cd2d990521891a8.tar.gz bcm5719-llvm-f431ad4477efef96da82f6ce8cd2d990521891a8.zip | |
Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patterns
that were overloaded to work before and after the stackifier runs. With the
new clean world, it is possible to write patterns for these instructions: woo!
This also adds a few simple patterns here and there, though there are a lot
still missing. These should be easy to add though. :)
See the comments under "Floating Point Stack Support" for more details on
the new world order.
This patch as absolutely no effect on the generated code, woo!
llvm-svn: 24899
Diffstat (limited to 'llvm/lib/Target/X86/X86RegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterInfo.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index a0e0aca16c2..765b657d065 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -56,7 +56,7 @@ void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, } else if (RC == &X86::R16RegClass) { Opc = X86::MOV16mr; } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { - Opc = X86::FST64m; + Opc = X86::FpST64m; } else if (RC == &X86::V4F4RegClass) { Opc = X86::MOVSSmr; } else if (RC == &X86::V2F8RegClass) { @@ -80,7 +80,7 @@ void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, } else if (RC == &X86::R16RegClass) { Opc = X86::MOV16rm; } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) { - Opc = X86::FLD64m; + Opc = X86::FpLD64m; } else if (RC == &X86::V4F4RegClass) { Opc = X86::MOVSSrm; } else if (RC == &X86::V2F8RegClass) { @@ -123,8 +123,7 @@ unsigned X86RegisterInfo::isLoadFromStackSlot(MachineInstr *MI, case X86::MOV8rm: case X86::MOV16rm: case X86::MOV32rm: - case X86::FLD64m: - case X86::FLD80m: + case X86::FpLD64m: case X86::MOVSSrm: case X86::MOVSDrm: if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() && |
