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path: root/llvm/lib/Target/X86/X86InstrInfo.cpp
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* [X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class.Craig Topper2019-06-181-7/+49
* [CodeGen] Add getMachineMemOperand + MachineMemOperand::Flags allocator helpe...Simon Pilgrim2019-06-131-8/+2
* [X86] Add VCMPSSZrr_Intk and VCMPSDZrr_Intk to isNonFoldablePartialRegisterLoad.Craig Topper2019-06-121-0/+2
* [X86] Add load folding isel patterns to scalar_math_patterns and AVX512_scala...Craig Topper2019-06-111-0/+1
* [SystemZ, RegAlloc] Favor 3-address instructions during instruction selection.Jonas Paulsson2019-06-081-1/+2
* [X86] Make masked floating point equality/ordered compares commutable for loa...Craig Topper2019-06-061-4/+14
* [X86] Add the vector integer min/max instructions to isAssociativeAndCommutat...Craig Topper2019-06-051-0/+84
* [X86] Add the SSE versions of PMULLW and PMULLD to isAssociativeAndCommutative.Craig Topper2019-06-021-0/+2
* [X86] Add VP2INTERSECT instructionsPengfei Wang2019-05-311-0/+8
* [X86-64] Fix 256-bit SET0 lowering for non-VLX targetsDavid Greene2019-05-281-0/+6
* Factor out redzone ABI checks [NFCI]Philip Reames2019-05-101-1/+1
* [X86] Reduce scope of variables where possible. NFCI.Simon Pilgrim2019-05-071-1/+1
* [X86] X86InstrInfo::findThreeSrcCommutedOpIndices - fix unread variable warning.Simon Pilgrim2019-05-061-1/+2
* [CodeGen] Add "const" to MachineInstr::mayAliasBjorn Pettersson2019-04-191-1/+1
* [X86] In CopyToFromAsymmetricReg, use VR128 instead of FR32 instructions for ...Craig Topper2019-04-171-12/+12
* [X86] Merge the different Jcc instructions for each condition code into singl...Craig Topper2019-04-051-59/+20
* [X86] Merge the different SETcc instructions for each condition code into sin...Craig Topper2019-04-051-64/+16
* [X86] Merge the different CMOV instructions for each condition code into sing...Craig Topper2019-04-051-185/+41
* [IR] Refactor attribute methods in Function class (NFC)Evandro Menezes2019-04-041-5/+5
* [X86] Mark the default case of the X86InstrInfo::convertToThreeAddress switch...Craig Topper2019-04-021-1/+1
* [X86] Add post-isel pseudos for rotate by immediate using SHLD/SHRDCraig Topper2019-03-271-0/+18
* [X86] Make ADD*_DB post-RA pseudos and expand them in expandPostRAPseudo.Craig Topper2019-03-181-0/+11
* [X86] Remove VCVTSI2SDZrrb_Int as it shouldn't exist.Craig Topper2019-03-111-1/+0
* [X86] Enable 8-bit SHL to convert to LEACraig Topper2019-03-051-0/+4
* [X86] Allow 8-bit INC/DEC to be converted to LEA.Craig Topper2019-03-051-2/+7
* [X86] Enable 8-bit OR with disjoint bits to convert to LEACraig Topper2019-03-051-9/+17
* [X86] Use X86::LAST_VALID_COND instead of assuming X86::COND_S is the last en...Craig Topper2019-02-281-1/+1
* Fix MSVC constant truncation warnings. NFCI.Simon Pilgrim2019-02-231-11/+11
* [X86] Sign extend the 8-bit immediate when commuting blend instructions to ma...Craig Topper2019-02-231-3/+5
* [X86] Don't prevent load folding for cvtsi2ss/cvtsi2sd based on hasPartialReg...Craig Topper2019-02-161-39/+48
* X86: Replace isSafeToClobberEFLAGS implementationMatt Arsenault2019-02-151-85/+1
* [X86] Remove isReMaterializable from X87 floating point constant loads and co...Craig Topper2019-02-081-1/+0
* [X86][AVX] Add VMOVDDUP-VPBROADCASTQ execution domain mappingSimon Pilgrim2019-02-011-0/+4
* Fix "comparison of unsigned expression >= 0 is always true" warning. NFCI.Simon Pilgrim2019-01-221-1/+1
* [X86][SSE] Add selective commutation support for insertps (PR40340)Simon Pilgrim2019-01-221-0/+22
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [X86] Don't allow optimizeCompareInstr to replace a CMP with BEXTR if the sig...Craig Topper2018-12-211-6/+18
* [X86] Add BSR to isUseDefConvertible.Craig Topper2018-12-181-6/+6
* [X86] Const correct some helper functions X86InstrInfo.cpp. NFCCraig Topper2018-12-181-6/+7
* [X86] Add T1MSKC and TZMSK to isDefConvertible used by optimizeCompareInstr.Craig Topper2018-12-171-0/+4
* [x86] allow 8-bit adds to be promoted by convertToThreeAddress() to form LEASanjay Patel2018-12-121-7/+18
* [x86] clean up code for converting 16-bit ops to LEA; NFCSanjay Patel2018-12-111-62/+57
* [x86] remove dead code for 16-bit LEA formation; NFCSanjay Patel2018-12-111-57/+13
* [x86] don't try to convert add with undef operands to LEASanjay Patel2018-12-091-36/+35
* [CodeGen][NFC] Make `TII::getMemOpBaseImmOfs` return a base operandFrancis Visoiu Mistrih2018-11-281-6/+7
* [TableGen] Refactor macro names (NFC)Evandro Menezes2018-11-271-1/+1
* LivePhysRegs/IfConversion: Change some types from unsigned to MCPhysReg; NFCMatthias Braun2018-11-061-1/+1
* Revert r345165 "[X86] Bring back the MOV64r0 pseudo instruction"Craig Topper2018-10-311-19/+4
* [tblgen][PredicateExpander] Add the ability to describe more complex constrai...Andrea Di Biagio2018-10-311-0/+3
* [ELF] Fix large code model MIR verifier errorsReid Kleckner2018-10-241-6/+22
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