summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/X86/X86ISelLowering.cpp
Commit message (Expand)AuthorAgeFilesLines
...
* Fix signed/unsigned comparison warning. NFC.Simon Pilgrim2019-08-041-1/+1
* [X86] SimplifyMultipleUseDemandedBits - Add target shuffle supportSimon Pilgrim2019-08-041-0/+46
* [X86] Consistently use MVT::i8 for the constant operand of BLENDI and INSERTP...Craig Topper2019-08-041-8/+8
* [x86] change free truncate hook to handle only simple types (PR42880)Sanjay Patel2019-08-031-0/+2
* Emit diagnostic if an inline asm constraint requires an immediateBill Wendling2019-08-031-2/+3
* [X86] Use the pointer VT for the Scale node when lowering x86 gather/scatter ...Craig Topper2019-08-021-4/+12
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-1/+1
* [X86] In decomposeMulByConstant, legalize the VT before querying whether the ...Craig Topper2019-08-011-2/+12
* [X86][SSE] Add PEXTR*(PINSR*(v, s, c), c) -> s combine.Simon Pilgrim2019-08-011-4/+15
* [X86][SSE] SimplifyMultipleUseDemandedBits - Add PEXTR/PINSR B+W handlingSimon Pilgrim2019-08-011-0/+27
* [X86] EltsFromConsecutiveLoads - don't attempt to merge volatile loads (PR42846)Simon Pilgrim2019-08-011-1/+4
* Revert "[MS] Emit S_HEAPALLOCSITE debug info in Selection DAG" andAmy Huang2019-07-311-11/+0
* [X86] Add DAG combine to fold any_extend_vector_inreg+truncstore to an extrac...Craig Topper2019-07-311-0/+35
* [X86] Moved IsNOT helper earlier. NFCI.Simon Pilgrim2019-07-311-28/+28
* [X86][AVX] Ensure chained subvector insertions are the same size (PR42833)Simon Pilgrim2019-07-311-0/+2
* [MS] Emit S_HEAPALLOCSITE debug info in SelectionDAGAmy Huang2019-07-311-0/+11
* [X86] Fix mistake in comment. NFCCraig Topper2019-07-301-2/+2
* [X86] SimplifyDemandedVectorEltsForTargetNode should be calling resolveTarget...Simon Pilgrim2019-07-301-0/+1
* [X86][AVX] SimplifyDemandedVectorElts - handle extraction from X86ISD::SUBV_B...Simon Pilgrim2019-07-301-8/+10
* [X86] Fix typo in comment. We're looking at a right shift not a left shift. NFCCraig Topper2019-07-291-1/+1
* [X86] resolveTargetShuffleInputs - add depth to limit recursion.Simon Pilgrim2019-07-291-15/+19
* [X86] combineX86ShufflesRecursively - start recursion at depth = 0. NFCI.Simon Pilgrim2019-07-291-18/+18
* [X86] Don't use PMADDWD for vector add reductions of multiplies if the mul in...Craig Topper2019-07-291-12/+22
* [X86] In combineLoopMAddPattern and combineLoopSADPattern, preserve the vecto...Craig Topper2019-07-281-78/+63
* [X86][SSE] Replace PMULDQ GetDemandedBits combine with SimplifyMultipleUseDem...Simon Pilgrim2019-07-271-9/+12
* Revert "[X86][SSE] Replace PMULDQ GetDemandedBits combine with SimplifyMultip...Vlad Tsyrklevich2019-07-261-12/+9
* [X86][SSE] Replace PMULDQ GetDemandedBits combine with SimplifyMultipleUseDem...Simon Pilgrim2019-07-261-9/+12
* [X86] concatSubVectors - remove unnecessary args. NFCI.Simon Pilgrim2019-07-251-9/+12
* [Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 foldRoman Lebedev2019-07-241-0/+27
* [DAGCombine] matchBinOpReduction - add partial reduction matchingSimon Pilgrim2019-07-241-9/+8
* [X86] In lowerVectorShuffle, instead of creating a new node to canonicalize t...Craig Topper2019-07-231-11/+15
* [X86] When using AND+PACKUS in lowerV16I8Shuffle, generate the build vector d...Craig Topper2019-07-221-5/+4
* [X86] EltsFromConsecutiveLoads - support common source loads (REAPPLIED)Simon Pilgrim2019-07-221-5/+62
* [X86] SimplifyDemandedVectorEltsForTargetNode - Move SUBV_BROADCAST narrowing...Simon Pilgrim2019-07-211-19/+13
* [X86][SSE] Use PSADBW to improve vXi8 sum reduction (PR42674)Simon Pilgrim2019-07-201-7/+38
* Revert [X86] EltsFromConsecutiveLoads - support common source loadsReid Kleckner2019-07-181-63/+5
* [X86] EltsFromConsecutiveLoads - support common source loadsSimon Pilgrim2019-07-181-5/+63
* [X86] Disable combineConcatVectors for vXi1 vectors.Craig Topper2019-07-181-0/+4
* [X86] Make sure we mark 128/256 MLOAD as Legal with VLX when min-legal-vector...Craig Topper2019-07-171-5/+7
* [x86] use more phadd for reductionsSanjay Patel2019-07-161-0/+54
* [X86] In combineStore, don't convert v2f32 load/store pairs to f64 loads/stores.Craig Topper2019-07-161-3/+2
* Fix parameter name comments using clang-tidy. NFC.Rui Ueyama2019-07-161-2/+2
* [x86] try to keep FP casted+truncated+extracted vector element out of GPRsSanjay Patel2019-07-151-0/+39
* [X86] Return UNDEF from LowerScalarImmediateShift when the shift amount is ou...Craig Topper2019-07-151-2/+5
* [X86] isTargetShuffleEquivalent - assert the expected mask is correctly forme...Simon Pilgrim2019-07-151-0/+2
* [X86] Separate the memory size of vzext_load/vextract_store from the element ...Craig Topper2019-07-151-26/+47
* [x86] simplify cmov with same true/false operandsSanjay Patel2019-07-131-0/+4
* [X86] Merge negated ISD::SUB nodes into X86ISD::SUB equivalent (PR40483)Sanjay Patel2019-07-111-7/+7
* [X86] Remove unused variable. NFCCraig Topper2019-07-101-1/+0
* [X86] EltsFromConsecutiveLoads - clean up element size calcs. NFCI.Simon Pilgrim2019-07-101-14/+12
OpenPOWER on IntegriCloud