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path: root/llvm/lib/Target/X86/X86CodeEmitter.cpp
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* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-1/+1
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Add support to the old JIT for acquire/release loads and stores on x86. ↵Eli Friedman2011-10-241-9/+24
| | | | | | PR11207. llvm-svn: 142841
* Add X86 RORX instructionCraig Topper2011-10-231-0/+2
| | | | llvm-svn: 142741
* Add X86 PEXTR and PDEP instructions.Craig Topper2011-10-161-5/+4
| | | | llvm-svn: 142141
* Remove premature previous commit.Nicolas Geoffray2011-08-281-25/+7
| | | | llvm-svn: 138725
* Encoding of instructions referencing segments has changed. Do what ↵Nicolas Geoffray2011-08-281-7/+25
| | | | | | X86MCCodeEmitter does. llvm-svn: 138723
* Explicitly cast narrowing conversions inside {}s that will become errors inJeffrey Yasskin2011-07-271-1/+1
| | | | | | C++0x. llvm-svn: 136211
* Refactor X86 target to separate MC code from Target code.Evan Cheng2011-07-251-1/+1
| | | | llvm-svn: 135930
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-181-19/+13
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-7/+7
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-041-0/+8
| | | | llvm-svn: 128826
* add jit support for the new psuedo instructions I added forChris Lattner2010-10-081-0/+14
| | | | | | | | | the add/or xform. The JIT isn't mcized yet, boo. This fixes Olden/voronoi, bh and a ton of other stuff that uses the jit. llvm-svn: 116125
* machine a mutable machineinstr down into emitInstruction.Chris Lattner2010-10-081-4/+3
| | | | llvm-svn: 116124
* tyopsGabor Greif2010-08-231-1/+1
| | | | llvm-svn: 111835
* More fixes for win64:Anton Korobeynikov2010-08-171-1/+2
| | | | | | | | - Do not clobber al during variadic calls, this is AMD64 ABI-only feature - Emit wincall64, where necessary Patch by Cameron Esfahani! llvm-svn: 111289
* Revert last patch and r110954 as I meant to.Eric Christopher2010-08-131-1/+0
| | | | llvm-svn: 111001
* Revert r110954 for now, pseudo instructions can't make it through to the JIT.Eric Christopher2010-08-131-0/+1
| | | | llvm-svn: 111000
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-2/+2
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-2/+2
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-2/+2
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Handle the memory barrier pseudo that goes to nothing for the JIT.Eric Christopher2010-08-051-1/+7
| | | | llvm-svn: 110371
* instead of migrating it to the MC instruction encoder, justChris Lattner2010-07-221-1/+98
| | | | | | | | | | | | | | rip out the implementation of X86InstrInfo::GetInstSizeInBytes. The code being ripped out just implemented a copy and hacked up version of the (old) instruction encoder, and is buggy and terrible in other ways. Since "GetInstSizeInBytes" is really only there to support the JIT's "NeedsExactSize" hook (which noone is using), just rip out the code. I will rip out the NeedsExactSize hook next. This resolves rdar://7617809 - switch X86InstrInfo::GetInstSizeInBytes to use X86MCCodeEmitter llvm-svn: 109149
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-161-1/+1
| | | | | | thus is a much more meaningful name. llvm-svn: 108563
* Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKillJakob Stoklund Olesen2010-07-161-1/+0
| | | | | | | | | pass that inserted it. It is no longer necessary to limit the live ranges of FP registers to a single basic block. llvm-svn: 108536
* Change LEA to have 5 operands for its memory operand, justChris Lattner2010-07-081-7/+1
| | | | | | | | | | | like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
* add some long-overdue enums to refer to the parts of the 5-operandChris Lattner2010-07-081-7/+7
| | | | | | X86 memory operand. llvm-svn: 107925
* Use pre-increment instead of post-increment when the result is not used.Dan Gohman2010-06-221-1/+1
| | | | llvm-svn: 106542
* Handle a displacement location in 64-bit as an RIP-relative displacement. ItBill Wendling2010-04-211-1/+11
| | | | | | | | | | | | | | | | | | fixes a bug (<rdar://problem/7880900>) in the JIT. This code wouldn't work: target triple = "x86_64-apple-darwin" define double @func(double %a) { %tmp1 = fmul double %a, 5.000000e-01 ; <double> [#uses=1] ret double %tmp1 } define i32 @main() nounwind { %1 = call double @func(double 4.770000e-04) ; <i64> [#uses=0] ret i32 0 } llvm-svn: 101965
* Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman2010-04-151-4/+6
| | | | llvm-svn: 101334
* rename llvm::llvm_report_error -> llvm::report_fatal_errorChris Lattner2010-04-071-1/+1
| | | | llvm-svn: 100709
* change the DBG_LABEL MachineInstr to always be createdChris Lattner2010-03-141-2/+0
| | | | | | with an MCSymbol instead of an immediate. llvm-svn: 98481
* switch GC_LABEL to use an MCSymbol operand instead of a label ID operand.Chris Lattner2010-03-141-1/+1
| | | | llvm-svn: 98474
* change the LabelSDNode to be EHLabelSDNode and make it holdChris Lattner2010-03-141-1/+4
| | | | | | | | an MCSymbol. Make the EH_LABEL MachineInstr hold its label with an MCSymbol instead of ID. Fix a bug in MMI.cpp which would return labels named "Label4" instead of "label4". llvm-svn: 98463
* change EH related stuff (other than EH_LABEL) to use MCSymbolChris Lattner2010-03-141-3/+4
| | | | | | | | | | | | | | | | instead of label ID's. This cleans up and regularizes a bunch of code and makes way for future progress. Unfortunately, this pointed out to me that JITDwarfEmitter.cpp is largely copy and paste from DwarfException/MachineModuleInfo and other places. This is very sad and disturbing. :( One major change here is that TidyLandingPads moved from being called in DwarfException::BeginFunction to being called in DwarfException::EndFunction. There should not be any functionality change from doing this, but I'm not an EH expert. llvm-svn: 98459
* rip out the 'heinous' x86 MCCodeEmitter implementation.Chris Lattner2010-02-131-333/+0
| | | | | | | We still have the templated X86 JIT emitter, *and* the almost-copy in X86InstrInfo for getting instruction sizes. llvm-svn: 96059
* Remove special cases for [LM]FENCE, MONITOR and MWAIT fromChris Lattner2010-02-121-21/+2
| | | | | | encoder and decoder by using new MRM_ forms. llvm-svn: 96048
* give MCCodeEmitters access to the current MCContext.Chris Lattner2010-02-121-3/+4
| | | | llvm-svn: 96038
* add a bunch of mod/rm encoding types for fixed mod/rm bytes.Chris Lattner2010-02-121-0/+21
| | | | | | | This will work better for the disassembler for modeling things like lfence/monitor/vmcall etc. llvm-svn: 95960
* dont' call getX86RegNum on X86::RIP, it doesn't like that. ThisChris Lattner2010-02-111-1/+3
| | | | | | fixes the remaining x86-64 jit failures afaik. llvm-svn: 95867
* fix a really nasty bug I introduced in r95693: r12 (and r12d, Chris Lattner2010-02-111-3/+6
| | | | | | | | | r12b, etc) also encodes to a R/M value of 4, which is just as illegal as ESP/RSP for the non-sib version an address. This fixes x86-64 jit miscompilations of a bunch of programs. llvm-svn: 95866
* MC: Switch MCFixup to just hold an MCExpr pointer instead of index into theDaniel Dunbar2010-02-101-4/+8
| | | | | | MCInst it came from. llvm-svn: 95767
* MC/X86: Add a dummy implementation of MCFixup generation for hacky X86 ↵Daniel Dunbar2010-02-091-8/+44
| | | | | | MCCodeEmitter. llvm-svn: 95709
* MC: First cut at MCFixup, for getting fixup/relocation information out of an ↵Daniel Dunbar2010-02-091-1/+20
| | | | | | MCCodeEmitter. llvm-svn: 95708
* fix X86 encoder to output [disp] only addresses with no SIB byteChris Lattner2010-02-091-73/+85
| | | | | | | | in X86-32 mode. This is still required in x86-64 mode to avoid forming [disp+rip] encoding. Rewrite the SIB byte decision logic to be actually understandable. llvm-svn: 95693
* revert r95689: getX86RegNum(BaseReg) != N86::ESP isChris Lattner2010-02-091-2/+2
| | | | | | a confusing idiom to check for ESP or RSP. llvm-svn: 95690
* simplify.Chris Lattner2010-02-091-2/+2
| | | | llvm-svn: 95689
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-6/+6
| | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
* wire up 64-bit MCCodeEmitter.Chris Lattner2010-02-051-2/+5
| | | | llvm-svn: 95438
* move functions for decoding X86II values into the X86II namespace.Chris Lattner2010-02-051-13/+13
| | | | llvm-svn: 95410
* change getSizeOfImm and getBaseOpcodeFor to just takeChris Lattner2010-02-051-13/+13
| | | | | | TSFlags directly instead of a TargetInstrDesc. llvm-svn: 95405
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