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path: root/llvm/lib/Target/X86/X86CodeEmitter.cpp
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* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-1/+1
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-5/+5
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Move TargetData to DataLayout.Micah Villmow2012-10-081-3/+3
| | | | llvm-svn: 165402
* Add register encoding support in X86 backendMichael Liao2012-10-041-15/+25
| | | | | | | | - Add 'HwEncoding' for X86 registers and call getEncodingValue() to retrieve their encoding values. - This's the first step to adopt new scheme. Furthur revising is onging. llvm-svn: 165241
* Remove code for setting the VEX L-bit as a function of operand size from the ↵Craig Topper2012-09-191-11/+0
| | | | | | code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. llvm-svn: 164204
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-221-3/+1
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
* Don't use implicit register operands to calculate L-bit for AVX ↵Craig Topper2012-07-201-0/+2
| | | | | | instructions. Needed because super reg defs and kills are added as implicit operands on 128-bit instructions. Fixes PR13349. Patch by Jose Fonseca. llvm-svn: 160543
* Update GATHER instructions to support 2 read-write operands. Patch from ↵Craig Topper2012-07-121-5/+15
| | | | | | myself and Manman Ren. llvm-svn: 160110
* Added FMA3 Intel instructions.Elena Demikhovsky2012-05-311-0/+3
| | | | | | | | I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks. I added tests for GodeGen and intrinsics. I did not change llvm.fma.f32/64 - it may be done later. llvm-svn: 157737
* Port support for SSE4a extrq/insertq to the old jit code emitter.Benjamin Kramer2012-05-301-1/+1
| | | | llvm-svn: 157685
* Fix indentation of wrapped line for readability. No functional change.Craig Topper2012-05-231-1/+1
| | | | llvm-svn: 157309
* Tidy up some spacing and inconsistent use of pre/post increment. No ↵Craig Topper2012-05-191-13/+13
| | | | | | functional change intended. llvm-svn: 157122
* Copy some AVX support from MCJIT to JIT. Maybe will fix PR12748.Craig Topper2012-05-191-17/+29
| | | | llvm-svn: 157109
* Remove unneeded break.Jakub Staszak2012-05-011-1/+0
| | | | llvm-svn: 155959
* Remove trailing spaces.Jakub Staszak2012-05-011-43/+43
| | | | llvm-svn: 155956
* Attempt to handle MRMInitReg in emitVEXOpcodePrefix. Hopefully fixes PR12711.Craig Topper2012-05-011-1/+12
| | | | llvm-svn: 155896
* Copied all the VEX prefix encoding code from X86MCCodeEmitter to the x86 JIT ↵Pete Cooper2012-04-301-96/+531
| | | | | | emitter. Needs some major refactoring as these two code emitters are almost identical llvm-svn: 155810
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Use the same CALL instructions for Windows as for everything else.Jakob Stoklund Olesen2012-02-161-2/+1
| | | | | | | The different calling conventions and call-preserved registers are represented with regmask operands that are added dynamically. llvm-svn: 150708
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-1/+1
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Add support to the old JIT for acquire/release loads and stores on x86. ↵Eli Friedman2011-10-241-9/+24
| | | | | | PR11207. llvm-svn: 142841
* Add X86 RORX instructionCraig Topper2011-10-231-0/+2
| | | | llvm-svn: 142741
* Add X86 PEXTR and PDEP instructions.Craig Topper2011-10-161-5/+4
| | | | llvm-svn: 142141
* Remove premature previous commit.Nicolas Geoffray2011-08-281-25/+7
| | | | llvm-svn: 138725
* Encoding of instructions referencing segments has changed. Do what ↵Nicolas Geoffray2011-08-281-7/+25
| | | | | | X86MCCodeEmitter does. llvm-svn: 138723
* Explicitly cast narrowing conversions inside {}s that will become errors inJeffrey Yasskin2011-07-271-1/+1
| | | | | | C++0x. llvm-svn: 136211
* Refactor X86 target to separate MC code from Target code.Evan Cheng2011-07-251-1/+1
| | | | llvm-svn: 135930
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-181-19/+13
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-7/+7
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-041-0/+8
| | | | llvm-svn: 128826
* add jit support for the new psuedo instructions I added forChris Lattner2010-10-081-0/+14
| | | | | | | | | the add/or xform. The JIT isn't mcized yet, boo. This fixes Olden/voronoi, bh and a ton of other stuff that uses the jit. llvm-svn: 116125
* machine a mutable machineinstr down into emitInstruction.Chris Lattner2010-10-081-4/+3
| | | | llvm-svn: 116124
* tyopsGabor Greif2010-08-231-1/+1
| | | | llvm-svn: 111835
* More fixes for win64:Anton Korobeynikov2010-08-171-1/+2
| | | | | | | | - Do not clobber al during variadic calls, this is AMD64 ABI-only feature - Emit wincall64, where necessary Patch by Cameron Esfahani! llvm-svn: 111289
* Revert last patch and r110954 as I meant to.Eric Christopher2010-08-131-1/+0
| | | | llvm-svn: 111001
* Revert r110954 for now, pseudo instructions can't make it through to the JIT.Eric Christopher2010-08-131-0/+1
| | | | llvm-svn: 111000
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-2/+2
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-2/+2
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-2/+2
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Handle the memory barrier pseudo that goes to nothing for the JIT.Eric Christopher2010-08-051-1/+7
| | | | llvm-svn: 110371
* instead of migrating it to the MC instruction encoder, justChris Lattner2010-07-221-1/+98
| | | | | | | | | | | | | | rip out the implementation of X86InstrInfo::GetInstSizeInBytes. The code being ripped out just implemented a copy and hacked up version of the (old) instruction encoder, and is buggy and terrible in other ways. Since "GetInstSizeInBytes" is really only there to support the JIT's "NeedsExactSize" hook (which noone is using), just rip out the code. I will rip out the NeedsExactSize hook next. This resolves rdar://7617809 - switch X86InstrInfo::GetInstSizeInBytes to use X86MCCodeEmitter llvm-svn: 109149
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-161-1/+1
| | | | | | thus is a much more meaningful name. llvm-svn: 108563
* Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKillJakob Stoklund Olesen2010-07-161-1/+0
| | | | | | | | | pass that inserted it. It is no longer necessary to limit the live ranges of FP registers to a single basic block. llvm-svn: 108536
* Change LEA to have 5 operands for its memory operand, justChris Lattner2010-07-081-7/+1
| | | | | | | | | | | like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
* add some long-overdue enums to refer to the parts of the 5-operandChris Lattner2010-07-081-7/+7
| | | | | | X86 memory operand. llvm-svn: 107925
* Use pre-increment instead of post-increment when the result is not used.Dan Gohman2010-06-221-1/+1
| | | | llvm-svn: 106542
* Handle a displacement location in 64-bit as an RIP-relative displacement. ItBill Wendling2010-04-211-1/+11
| | | | | | | | | | | | | | | | | | fixes a bug (<rdar://problem/7880900>) in the JIT. This code wouldn't work: target triple = "x86_64-apple-darwin" define double @func(double %a) { %tmp1 = fmul double %a, 5.000000e-01 ; <double> [#uses=1] ret double %tmp1 } define i32 @main() nounwind { %1 = call double @func(double 4.770000e-04) ; <i64> [#uses=0] ret i32 0 } llvm-svn: 101965
* Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman2010-04-151-4/+6
| | | | llvm-svn: 101334
* rename llvm::llvm_report_error -> llvm::report_fatal_errorChris Lattner2010-04-071-1/+1
| | | | llvm-svn: 100709
* change the DBG_LABEL MachineInstr to always be createdChris Lattner2010-03-141-2/+0
| | | | | | with an MCSymbol instead of an immediate. llvm-svn: 98481
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