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* Re-apply r211399, "Generate native unwind info on Win64" with a fix to ↵NAKAMURA Takumi2014-06-251-0/+10
| | | | | | | | | | | | | | | | | | | | | | | ignore SEH pseudo ops in X86 JIT emitter. -- This patch enables LLVM to emit Win64-native unwind info rather than DWARF CFI. It handles all corner cases (I hope), including stack realignment. Because the unwind info is not flexible enough to describe stack frames with a gap of unknown size in the middle, such as the one caused by stack realignment, I modified register spilling code to place all spills into the fixed frame slots, so that they can be accessed relative to the frame pointer. Patch by Vadim Chugunov! Reviewed By: rnk Differential Revision: http://reviews.llvm.org/D4081 llvm-svn: 211691
* Two small enhancements for the JIT.Yaron Keren2014-06-041-1/+6
| | | | | | | | | | When JITting a large project such as Boost it's quite hard to figure out the problematic inline asm without debug location. This patch provides debug location printout before the JIT aborts due to inline asm. printDebugLoc() was exposed from MachineInstr.cpp and reused here. If the JIT run with debug info, don't bomb on DBG_VALUE but ignore them. http://reviews.llvm.org/D3416 llvm-svn: 210201
* [C++] Use 'nullptr'.Craig Topper2014-04-281-1/+1
| | | | llvm-svn: 207394
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-2/+2
| | | | llvm-svn: 207197
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-091-3/+3
| | | | | | class. llvm-svn: 203378
* Replace PROLOG_LABEL with a new CFI_INSTRUCTION.Rafael Espindola2014-03-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | The old system was fairly convoluted: * A temporary label was created. * A single PROLOG_LABEL was created with it. * A few MCCFIInstructions were created with the same label. The semantics were that the cfi instructions were mapped to the PROLOG_LABEL via the temporary label. The output position was that of the PROLOG_LABEL. The temporary label itself was used only for doing the mapping. The new CFI_INSTRUCTION has a 1:1 mapping to MCCFIInstructions and points to one by holding an index into the CFI instructions of this function. I did consider removing MMI.getFrameInstructions completelly and having CFI_INSTRUCTION own a MCCFIInstruction, but MCCFIInstructions have non trivial constructors and destructors and are somewhat big, so the this setup is probably better. The net result is that we don't create temporary labels that are never used. llvm-svn: 203204
* Remove special FP opcode maps and instead add enough MRM_XX formats to ↵Craig Topper2014-02-191-8/+34
| | | | | | handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change. llvm-svn: 201649
* Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of ↵Craig Topper2014-02-191-16/+11
| | | | | | 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. llvm-svn: 201641
* Recommit r201059 and r201060 with hopefully a fix for its original failure.Craig Topper2014-02-101-2/+7
| | | | | | | | | | Original commits messages: Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. llvm-svn: 201065
* Revert r201059 and r201060.Bob Wilson2014-02-101-6/+2
| | | | | | | | r201059 appears to cause a crash in a bootstrapped build of clang. Craig isn't available to look at it right now, so I'm reverting it while he investigates. llvm-svn: 201064
* Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' ↵Craig Topper2014-02-101-2/+6
| | | | | | field of modrm byte as a don't care value. Will allow for simplification of disassembler code. llvm-svn: 201059
* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ↵Craig Topper2014-02-021-1/+1
| | | | | | meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
* Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field ↵Craig Topper2014-02-021-8/+14
| | | | | | in TSFlags. llvm-svn: 200624
* Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the ↵Craig Topper2014-01-311-102/+52
| | | | | | TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters. llvm-svn: 200522
* Move REP out of the Prefix field of the X86 format. Give it its own bit. It ↵Craig Topper2014-01-311-2/+1
| | | | | | had special handling anyway and this enables a future patch. llvm-svn: 200520
* Move address override handling in X86CodeEmitter to a place where it works ↵Craig Topper2014-01-311-28/+28
| | | | | | for VEX encoded instructions too. This allows 32-bit addressing to work in 64-bit mode. llvm-svn: 200517
* Remove use of OpSize for populating VEX_PP field. A prefix encoding is now ↵Craig Topper2014-01-161-10/+4
| | | | | | used instead. Simplify some other code. No functional changes intended. llvm-svn: 199353
* Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix ↵Craig Topper2014-01-141-0/+19
| | | | | | | | and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke. llvm-svn: 199193
* Remove SegOvrBits from X86 TSFlags since they weren't being used.Craig Topper2014-01-061-23/+13
| | | | llvm-svn: 198588
* Add missing MRM_XX forms to the old JIT emitter for consistency.Craig Topper2013-12-311-26/+39
| | | | llvm-svn: 198258
* Remove MRMInitReg form now that it's last use is gone.Craig Topper2013-12-311-24/+0
| | | | llvm-svn: 198257
* Change type of XOP flag in code emitters to a bool. Remove a some unneeded ↵Craig Topper2013-09-291-7/+4
| | | | | | cases from switch. llvm-svn: 191632
* Add comments for XOPA map introduced with TBM instructions.aCraig Topper2013-09-291-1/+2
| | | | llvm-svn: 191630
* Adding intrinsics to the llvm backend for TBM instruction set.Yunzhong Gao2013-09-271-0/+3
| | | | | | Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
* Synchronize VEX JIT encoding code with the MCJIT version. Fix a bug in the ↵Craig Topper2013-08-211-11/+10
| | | | | | MCJIT code where CurOp was being incremented even if the operand it was pointing at wasn't used. Maybe only matters if there are any EVEX_K instructions that aren't VEX_4V. llvm-svn: 188868
* In LLVM FMA3 operands are dst, src1, src2, src3, however dst is not encoded ↵Nadav Rotem2013-08-211-2/+8
| | | | | | | | as it is always src1. This was causing the encoding of the operands to be off by one. Patch by Chris Bieneman. llvm-svn: 188866
* Remove unused c'tor.Bill Wendling2013-06-071-7/+2
| | | | llvm-svn: 183570
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-06-011-1/+1
| | | | | | | | | | | | | | The MOV64ri64i32 instruction required hacky MCInst lowering because it was allocated as setting a GR64, but the eventual instruction ("movl") only set a GR32. This converts it into a so-called "MOV32ri64" which still accepts a (appropriate) 64-bit immediate but defines a GR32. This is then converted to the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy. This fixes a typo in the opcode field of the original patch, which should make the legact JIT work again (& adds test for that problem). llvm-svn: 183068
* Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as itEric Christopher2013-05-311-1/+1
| | | | | | seems to have caused PR16192 and other JIT related failures. llvm-svn: 183059
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-05-311-1/+1
| | | | | | | | | | The MOV64ri64i32 instruction required hacky MCInst lowering because it was allocated as setting a GR64, but the eventual instruction ("movl") only set a GR32. This converts it into a so-called "MOV32ri64" which still accepts a (appropriate) 64-bit immediate but defines a GR32. This is then converted to the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy. llvm-svn: 182991
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-111-0/+8
| | | | | | | As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. llvm-svn: 179266
* Add X86 code emitter support AVX encoded MRMDestReg instructions.Craig Topper2013-03-161-4/+15
| | | | | | Previously we weren't skipping the VVVV encoded register. Based on patch by Michael Liao. llvm-svn: 177221
* Fix the name of a variable to match its declaration. Fixes build failure ↵Craig Topper2013-03-141-1/+1
| | | | | | from r177014. llvm-svn: 177015
* Fix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit ↵Craig Topper2013-03-141-0/+5
| | | | | | set. The VEX.B was being calculated from the wrong operand. Fixes at least some portion of PR14185. llvm-svn: 177014
* Fix commentsEli Bendersky2013-02-051-1/+1
| | | | llvm-svn: 174390
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-1/+1
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-5/+5
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Move TargetData to DataLayout.Micah Villmow2012-10-081-3/+3
| | | | llvm-svn: 165402
* Add register encoding support in X86 backendMichael Liao2012-10-041-15/+25
| | | | | | | | - Add 'HwEncoding' for X86 registers and call getEncodingValue() to retrieve their encoding values. - This's the first step to adopt new scheme. Furthur revising is onging. llvm-svn: 165241
* Remove code for setting the VEX L-bit as a function of operand size from the ↵Craig Topper2012-09-191-11/+0
| | | | | | code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. llvm-svn: 164204
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-221-3/+1
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
* Don't use implicit register operands to calculate L-bit for AVX ↵Craig Topper2012-07-201-0/+2
| | | | | | instructions. Needed because super reg defs and kills are added as implicit operands on 128-bit instructions. Fixes PR13349. Patch by Jose Fonseca. llvm-svn: 160543
* Update GATHER instructions to support 2 read-write operands. Patch from ↵Craig Topper2012-07-121-5/+15
| | | | | | myself and Manman Ren. llvm-svn: 160110
* Added FMA3 Intel instructions.Elena Demikhovsky2012-05-311-0/+3
| | | | | | | | I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks. I added tests for GodeGen and intrinsics. I did not change llvm.fma.f32/64 - it may be done later. llvm-svn: 157737
* Port support for SSE4a extrq/insertq to the old jit code emitter.Benjamin Kramer2012-05-301-1/+1
| | | | llvm-svn: 157685
* Fix indentation of wrapped line for readability. No functional change.Craig Topper2012-05-231-1/+1
| | | | llvm-svn: 157309
* Tidy up some spacing and inconsistent use of pre/post increment. No ↵Craig Topper2012-05-191-13/+13
| | | | | | functional change intended. llvm-svn: 157122
* Copy some AVX support from MCJIT to JIT. Maybe will fix PR12748.Craig Topper2012-05-191-17/+29
| | | | llvm-svn: 157109
* Remove unneeded break.Jakub Staszak2012-05-011-1/+0
| | | | llvm-svn: 155959
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