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* Remove use of OpSize for populating VEX_PP field. A prefix encoding is now ↵Craig Topper2014-01-161-10/+4
| | | | | | used instead. Simplify some other code. No functional changes intended. llvm-svn: 199353
* Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix ↵Craig Topper2014-01-141-0/+19
| | | | | | | | and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke. llvm-svn: 199193
* AVX-512: Embedded Rounding Control - encoding and printingElena Demikhovsky2014-01-131-9/+15
| | | | | | Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC. llvm-svn: 199102
* [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understandDavid Woodhouse2014-01-081-4/+9
| | | | | | | | | | It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
* [x86] Use 16-bit addressing where possible in 16-bit modeDavid Woodhouse2014-01-081-14/+18
| | | | | | | | | Where "where possible" means that it's an immediate value and it's below 0x10000. In fact GAS will either truncate or error with larger values, and will insist on using the addr32 prefix to get 32-bit addressing. So perhaps we should do that, in a later patch. llvm-svn: 198758
* [x86] Fix JCXZ,JECXZ_32 for 16-bit modeDavid Woodhouse2014-01-081-1/+5
| | | | | | | JCXZ should have the 0x67 prefix only if we're in 32-bit mode, so make that appropriately conditional. And JECXZ needs the prefix instead. llvm-svn: 198757
* Remove SegOvrBits from X86 TSFlags since they weren't being used.Craig Topper2014-01-061-23/+13
| | | | llvm-svn: 198588
* Remove argument to fix build bot failure.Craig Topper2014-01-061-1/+1
| | | | llvm-svn: 198587
* Add OpSize16 bit, for instructions which need 0x66 prefix in 16-bit modeCraig Topper2014-01-061-2/+1
| | | | | | | | | | | | | | | | | The 0x66 prefix toggles between 16-bit and 32-bit addressing mode. So in 32-bit mode it is used to switch to 16-bit addressing mode for the following instruction, while in 16-bit mode it's the other way round — it's used to switch to 32-bit mode instead. Thus, emit the 0x66 prefix byte for OpSize only in 32-bit (and 64-bit) mode, and introduce a new OpSize16 bit which is used in 16-bit mode instead. This is just the basic infrastructure for that change; a subsequent patch will add the new OpSize16 bit to the 32-bit instructions that need it. Patch from David Woodhouse. llvm-svn: 198586
* [x86] Add basic support for .code16Craig Topper2014-01-061-2/+10
| | | | | | | | | | | This is not really expected to work right yet. Mostly because we will still emit the OpSize (0x66) prefix in all the wrong places, along with a number of other corner cases. Those will all be fixed in the subsequent commits. Patch from David Woodhouse. llvm-svn: 198584
* Fix ModR/M byte output for 16-bit addressing modes (PR18220)Craig Topper2014-01-051-0/+60
| | | | | | | | | Add some tests to validate correct register selection, including a fix to an existing test which was requiring the *wrong* output. Patch from David Woodhouse. llvm-svn: 198566
* AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmpElena Demikhovsky2014-01-011-8/+29
| | | | | | | Printing rounding control. Enncoding for EVEX_RC (rounding control). llvm-svn: 198277
* Remove MRMInitReg form now that it's last use is gone.Craig Topper2013-12-311-4/+0
| | | | llvm-svn: 198257
* Merge case statements to remove redundant code.Craig Topper2013-12-301-18/+12
| | | | llvm-svn: 198241
* Change type of XOP flag in code emitters to a bool. Remove a some unneeded ↵Craig Topper2013-09-291-7/+4
| | | | | | cases from switch. llvm-svn: 191632
* Add comments for XOPA map introduced with TBM instructions.aCraig Topper2013-09-291-1/+2
| | | | llvm-svn: 191630
* Adding intrinsics to the llvm backend for TBM instruction set.Yunzhong Gao2013-09-271-0/+3
| | | | | | Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
* AVX-512: Added masked SHIFT commands, more encoding testsElena Demikhovsky2013-08-221-5/+6
| | | | llvm-svn: 189005
* Synchronize VEX JIT encoding code with the MCJIT version. Fix a bug in the ↵Craig Topper2013-08-211-1/+1
| | | | | | MCJIT code where CurOp was being incremented even if the operand it was pointing at wasn't used. Maybe only matters if there are any EVEX_K instructions that aren't VEX_4V. llvm-svn: 188868
* EVEX and compressed displacement encoding for AVX512Elena Demikhovsky2013-08-011-47/+268
| | | | llvm-svn: 187576
* Use pointers to the MCAsmInfo and MCRegInfo.Bill Wendling2013-06-181-1/+1
| | | | | | | | | Someone may want to do something crazy, like replace these objects if they change or something. No functionality change intended. llvm-svn: 184175
* Fix section relocation for SECTIONREL32 with immediate offset.Rafael Espindola2013-04-251-2/+15
| | | | | | Patch by Kai Nacke. This matches the gnu as output. llvm-svn: 180568
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-111-6/+9
| | | | | | | As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. llvm-svn: 179266
* In the X86 back end, getMemoryOperandNo() returns the offsetPreston Gurd2013-04-101-11/+1
| | | | | | | | | | | | into the operand array of the start of the memory reference descriptor. Additional code in EncodeInstruction provides an additional adjustment. This patch places that additional code in a separate function, called getOperandBias, so that any caller of getMemoryOperandNo can also call getOperandBias. llvm-svn: 179211
* x86 -- add the XTEST instructionDave Zarzycki2013-03-251-10/+8
| | | | llvm-svn: 177888
* Add X86 code emitter support AVX encoded MRMDestReg instructions.Craig Topper2013-03-161-4/+15
| | | | | | Previously we weren't skipping the VVVV encoded register. Based on patch by Michael Liao. llvm-svn: 177221
* Fix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit ↵Craig Topper2013-03-141-0/+8
| | | | | | set. The VEX.B was being calculated from the wrong operand. Fixes at least some portion of PR14185. llvm-svn: 177014
* Add support of RTM from TSX extensionMichael Liao2012-11-081-7/+8
| | | | | | | | - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region llvm-svn: 167573
* Add register encoding support in X86 backendMichael Liao2012-10-041-4/+5
| | | | | | | | - Add 'HwEncoding' for X86 registers and call getEncodingValue() to retrieve their encoding values. - This's the first step to adopt new scheme. Furthur revising is onging. llvm-svn: 165241
* Remove code for setting the VEX L-bit as a function of operand size from the ↵Craig Topper2012-09-191-9/+0
| | | | | | code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. llvm-svn: 164204
* Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.Craig Topper2012-09-151-2/+2
| | | | llvm-svn: 163974
* Update GATHER instructions to support 2 read-write operands. Patch from ↵Craig Topper2012-07-121-5/+14
| | | | | | myself and Manman Ren. llvm-svn: 160110
* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-261-1/+6
| | | | | | | | | | | | Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. llvm-svn: 159221
* Added FMA3 Intel instructions.Elena Demikhovsky2012-05-311-2/+6
| | | | | | | | I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks. I added tests for GodeGen and intrinsics. I did not change llvm.fma.f32/64 - it may be done later. llvm-svn: 157737
* Add intrinsics, code gen, assembler and disassembler support for the SSE4a ↵Benjamin Kramer2012-05-291-2/+3
| | | | | | | | | | | extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. llvm-svn: 157634
* Tidy up some spacing and inconsistent use of pre/post increment. No ↵Craig Topper2012-05-191-15/+15
| | | | | | functional change intended. llvm-svn: 157122
* Allow MCCodeEmitter access to the target MCRegisterInfo.Jim Grosbach2012-05-151-0/+1
| | | | | | | | Add the MCRegisterInfo to the factories and constructors. Patch by Tom Stellard <Tom.Stellard@amd.com>. llvm-svn: 156828
* Put Is64BitMemOperand into !defined(NDEBUG) for now.Joerg Sonnenberger2012-03-211-0/+2
| | | | llvm-svn: 153185
* Fix generation of the address size override prefix. Add assertions forJoerg Sonnenberger2012-03-211-5/+51
| | | | | | | the invalid cases. At least 16bit operand in 64bit mode is currently not rejected in the parser. llvm-svn: 153166
* Add vmfunc instruction to X86 assembler and disassembler.Craig Topper2012-02-191-6/+8
| | | | llvm-svn: 150899
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Add X86 assembler and disassembler support for AMD SVM instructions. ↵Craig Topper2012-02-181-46/+36
| | | | | | Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. llvm-svn: 150873
* Add support for implicit TLS model used with MS VC runtime.Anton Korobeynikov2012-02-111-0/+6
| | | | | | Patch by Kai Nacke! llvm-svn: 150307
* Convert assert(0) to llvm_unreachable in X86 Target directory.Craig Topper2012-02-051-9/+9
| | | | llvm-svn: 149809
* Keep source location information for X86 MCFixup's.Jim Grosbach2012-01-271-18/+20
| | | | llvm-svn: 149106
* Separate the concept of having memory access in operand 4 from the concept ↵Craig Topper2011-12-301-15/+8
| | | | | | of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. llvm-svn: 147366
* XOP encoding bits and logic.Jan Sjödin2011-12-121-4/+28
| | | | llvm-svn: 146397
* Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gasRafael Espindola2011-12-101-12/+28
| | | | | | | | does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC, but it doesn't change the immediate in the same way as when the expression has no right hand side symbol. llvm-svn: 146311
* Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this ↵Jan Sjödin2011-12-081-11/+8
| | | | | | and fix the encoding. llvm-svn: 146151
* This patch contains support for encoding FMA4 instructions andBruno Cardoso Lopes2011-11-251-5/+29
| | | | | | | | | tablegen patterns for scalar FMA4 operations and intrinsic. Also add tests for vfmaddsd. Patch by Jan Sjodin llvm-svn: 145133
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