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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2012-05-29 19:05:25 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2012-05-29 19:05:25 +0000 |
| commit | ef479ea85459c5fc556bc2a09a4ab3efb9816381 (patch) | |
| tree | e3a6ef817fe7406a18e852a7ac2c0b6d29bd4ef8 /llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | |
| parent | a16b7fd029dfd20f52352c8c10060d794dec26db (diff) | |
| download | bcm5719-llvm-ef479ea85459c5fc556bc2a09a4ab3efb9816381.tar.gz bcm5719-llvm-ef479ea85459c5fc556bc2a09a4ab3efb9816381.zip | |
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.
llvm-svn: 157634
Diffstat (limited to 'llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index 24ac52d8e42..f79073ff588 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -1150,8 +1150,9 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, } // If there is a remaining operand, it must be a trailing immediate. Emit it - // according to the right size for the instruction. - if (CurOp != NumOps) { + // according to the right size for the instruction. Some instructions + // (SSE4a extrq and insertq) have two trailing immediates. + while (CurOp != NumOps && NumOps - CurOp <= 2) { // The last source register of a 4 operand instruction in AVX is encoded // in bits[7:4] of a immediate byte. if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) { |
