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* MC: Separate creating a generic object writer from creating a target object ↵Peter Collingbourne2018-05-213-10/+8
| | | | | | | | | | | | | writer. NFCI. With this we gain a little flexibility in how the generic object writer is created. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47045 llvm-svn: 332868
* MC: Change MCAsmBackend::writeNopData() to take a raw_ostream instead of an ↵Peter Collingbourne2018-05-211-5/+4
| | | | | | | | | | | | | MCObjectWriter. NFCI. To make this work I needed to add an endianness field to MCAsmBackend so that writeNopData() implementations know which endianness to use. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47035 llvm-svn: 332857
* [SystemZ] Fix commit message of previous commit.Jonas Paulsson2018-05-181-1/+1
| | | | | | | | | | | | | Sorry, the commit comment for r332703 is completely broken. My mind slipped - the right description would be: In SystemZDAGToDAGISel::Select(), in the handling for SELECT_CCMASK: Check if UpdateNodeOperands() returns a different SDNode and in that case call ReplaceNode. Review: Ulrich Weigand. llvm-svn: 332706
* [SystemZ] Fold AHIMux in foldMemoryOperandImpl.Jonas Paulsson2018-05-181-1/+7
| | | | | | | AHIMux can be folded the same way as AHI. Review: Ulrich Weigand llvm-svn: 332703
* [SystemZ] Commenting (NFC)Jonas Paulsson2018-05-172-6/+10
| | | | | | | Some minor commenting in scheduler files. Review: Ulrich Weigand llvm-svn: 332599
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-143-51/+44
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-093-4/+4
| | | | | | | | | | | | | | | | | | Because we create a new kind of debug instruction, DBG_LABEL, we need to check all passes which use isDebugValue() to check MachineInstr is debug instruction or not. When expelling debug instructions, we should expel both DBG_VALUE and DBG_LABEL. So, I create a new function, isDebugInstr(), in MachineInstr to check whether the MachineInstr is debug instruction or not. This patch has no new test case. I have run regression test and there is no difference in regression test. Differential Revision: https://reviews.llvm.org/D45342 Patch by Hsiangkai Wang. llvm-svn: 331844
* [SystemZ] Bugfix for MVCLoop CC clobbering.Jonas Paulsson2018-05-071-1/+1
| | | | | | | | MVCLoop clobbers CC (since it emits a compare/branch), but this was not modelled. Review: Ulrich Weigand llvm-svn: 331627
* Fix a bunch of places where operator-> was used directly on the return from ↵Craig Topper2018-05-052-4/+4
| | | | | | | | | | dyn_cast. Inspired by r331508, I did a grep and found these. Mostly just change from dyn_cast to cast. Some cases also showed a dyn_cast result being converted to bool, so those I changed to isa. llvm-svn: 331577
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-012-4/+4
| | | | | | | | | | | | | | | | We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
* [SystemZ] Handle SADDO et.al. and ADD/SUBCARRYUlrich Weigand2018-04-308-77/+614
| | | | | | | | | | | | | | | | This provides an optimized implementation of SADDO/SSUBO/UADDO/USUBO as well as ADDCARRY/SUBCARRY on top of the new CC implementation. In particular, multi-word arithmetic now uses UADDO/ADDCARRY instead of the old ADDC/ADDE logic, which means we no longer need to use "glue" links for those instructions. This also allows making full use of the memory-based instructions like ALSI, which couldn't be recognized due to limitations in the DAG matcher previously. Also, the llvm.sadd.with.overflow et.al. intrinsincs now expand to directly using the ADD instructions and checking for a CC 3 result. llvm-svn: 331203
* [SystemZ] Do not use glue to represent condition code dependenciesUlrich Weigand2018-04-3011-242/+494
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, an instruction setting the condition code is linked to the instruction using the condition code via a "glue" link in the SelectionDAG. This has a number of drawbacks; in particular, it means the same CC cannot be used by multiple users. It also makes it more difficult to efficiently implement SADDO et. al. This patch changes the back-end to represent CC dependencies as normal values during SelectionDAG matching, along the lines of how this is handled in the X86 back-end already. In addition to the core mechanics of updating all relevant patterns, this requires a number of additional changes: - We now need to be able to spill/restore a CC value into a GPR if necessary. This means providing a copyPhysReg implementation for moves involving CC, and defining getCrossCopyRegClass. - Since we still prefer to avoid such spills, we provide an override for IsProfitableToFold to avoid creating a merged LOAD / ICMP if this would result in multiple users of the CC. - combineCCMask no longer requires a single CC user, and no longer need to be careful about preventing invalid glue/chain cycles. - emitSelect needs to be more careful in marking CC live-in to the basic block it generates. Also, we can now optimize the case of multiple subsequent selects with the same condition just like X86 does. llvm-svn: 331202
* [SystemZ] Refactor some VT casts in DAG match patternsUlrich Weigand2018-04-301-59/+59
| | | | | | | | | | | | | | In patterns where we need to specify a result VT, prefer [(set (tr.vt tr.op:$V1), (operator ...))] over [(set tr.op:$V1, (tr.vt (operator ...)))] This is NFC now, but simplifies some future changes. llvm-svn: 331192
* [SystemZ] Improve handling of Select pseudo-instructionsUlrich Weigand2018-04-306-26/+22
| | | | | | | | | | | | | | | If we have LOCR instructions, select them directly from SelectionDAG instead of first going through a pseudo instruction and then using the custom inserter to emit the LOCR. Provide Select pseudo-instructions for VR32/VR64 if we have vector instructions, to avoid having to go through the first 16 FPRs unnecessarily. If we do not have LOCFHR, prefer using LOCR followed by a move over a conditional branch. llvm-svn: 331191
* [SystemZ] Remove scheduling info from some Pseudo instructions (NFC).Jonas Paulsson2018-04-277-133/+22
| | | | | | | | If the MachineInstr uses a custom inserter and is then erased after instruction selection, there is no use for mapping it to a sched class. Review: Ulrich Weigand llvm-svn: 331040
* [SystemZ] Use preferred 16-byte function alignmentUlrich Weigand2018-04-241-0/+2
| | | | | | | | While not necessary for correctness, it is preferable for performance reasons on all architectures we currently support to align functions to 16-byte boundaries by default. llvm-svn: 330718
* Consistently sort add_subdirectory calls in lib/Target/*/CMakeLists.txtNico Weber2018-04-231-1/+1
| | | | llvm-svn: 330584
* [SystemZ] Use ResourceCycles=30 for FPd unit (NFC).Jonas Paulsson2018-04-122-22/+4
| | | | | | | This is better than listing FPd 30 times :-) Review: Ulrich Weigand llvm-svn: 329887
* [SystemZ] Remove FullInstRWOverlapCheck from SchedMachineModels.Jonas Paulsson2018-04-124-18/+10
| | | | | | | | This is NFC, even though it caught just a few cases of overlapping regular expressions. Review: Ulrich Weigand llvm-svn: 329886
* [TargetSchedule] shrink interface for init(); NFCISanjay Patel2018-04-081-1/+1
| | | | | | | | | | The TargetSchedModel is always initialized using the TargetSubtargetInfo's MCSchedModel and TargetInstrInfo, so we don't need to extract those and pass 3 parameters to init(). Differential Revision: https://reviews.llvm.org/D44789 llvm-svn: 329540
* Sort targetgen calls in lib/Target/*/CMakeLists.Nico Weber2018-04-041-1/+2
| | | | | | | | | | | Makes it easier to see mistakes such as the one fixed in r329178 and makes the different target CMakeLists more consistent. Also remove some stale-looking comments from the Nios2 target cmakefile. No intended behavior change. llvm-svn: 329181
* Move TargetLoweringObjectFile from CodeGen to Target to fix layeringDavid Blaikie2018-03-231-1/+1
| | | | | | | It's implemented in Target & include from other Target headers, so the header should be in Target. llvm-svn: 328392
* [DAG, X86] Fix ISel-time node insertion idsNirav Dave2018-03-221-5/+5
| | | | | | | | | | | | | | | | As in SystemZ backend, correctly propagate node ids when inserting new unselected nodes into the DAG during instruction Seleciton for X86 target. Fixes PR36865. Reviewers: jyknight, craig.topper Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D44797 llvm-svn: 328233
* [DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"Nirav Dave2018-03-191-6/+9
| | | | | | | Reland ISel cycle checking improvements after simplifying node id invariant traversal and correcting typo. llvm-svn: 327898
* TableGen: Check the dynamic type of !cast<Rec>(string)Nicolai Haehnle2018-03-191-6/+6
| | | | | | | | | | | | | | | | | | | | | Summary: The docs already claim that this happens, but so far it hasn't. As a consequence, existing TableGen files get this wrong a lot, but luckily the fixes are all reasonably straightforward. To make this work with all the existing forms of self-references (since the true type of a record is only built up over time), the lookup of self-references in !cast is delayed until the final resolving step. Change-Id: If5923a72a252ba2fbc81a889d59775df0ef31164 Reviewers: arsenm, craig.topper, tra, MartinO Subscribers: wdng, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D44475 llvm-svn: 327849
* [SystemZ] Bugfix of CC liveness in emitMemMemWrapper (CLC).Jonas Paulsson2018-03-191-0/+4
| | | | | | | | | If DoneMBB becomes empty it must have CC added to its live-in list, since it will fall-through into EndMBB. This happens when the CLC loop does the complete range. Review: Ulrich Weigand llvm-svn: 327834
* [TableGen] When trying to reuse a scheduler class for instructions from an ↵Craig Topper2018-03-184-0/+12
| | | | | | | | | | | | InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. This is similar to the check later when we remap some of the instructions from one class to a new one. But if we reuse the class we don't get to do that check. So many CPUs have violations of this check that I had to add a flag to the SchedMachineModel to allow it to be disabled. Hopefully we can get those cleaned up quickly and remove this flag. A lot of the violations are due to overlapping regular expressions, but that's not the only kind of issue it found. llvm-svn: 327808
* Revert "[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172""Nirav Dave2018-03-171-9/+6
| | | | | | as it times out building test-suite on PPC. llvm-svn: 327778
* [DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"Nirav Dave2018-03-171-6/+9
| | | | | | | Reland ISel cycle checking improvements after simplifying and reducing node id invariant traversal. llvm-svn: 327777
* [SystemZ] computeKnownBitsForTargetNode() / ComputeNumSignBitsForTargetNode()Jonas Paulsson2018-03-172-19/+295
| | | | | | | | | | | Improve/implement these methods to improve DAG combining. This mainly concerns intrinsics. Some constant operands to SystemZISD nodes have been marked Opaque to avoid transforming back and forth between generic and target nodes infinitely. Review: Ulrich Weigand llvm-svn: 327765
* [SystemZ] Make AnyRegBitRegClass unallocatable.Jonas Paulsson2018-03-161-1/+1
| | | | | | | | AnyReg is just for the assembler and it is better to have it as not allocatable in order to simplify (make more intuitive) the RegPressureSets. Review: Ulrich Weigand llvm-svn: 327715
* TargetMachine: Add address space to getPointerSizeMatt Arsenault2018-03-141-1/+1
| | | | llvm-svn: 327467
* Revert: r327172 "Correct load-op-store cycle detection analysis"Nirav Dave2018-03-101-9/+6
| | | | | | | | | | r327171 "Improve Dependency analysis when doing multi-node Instruction Selection" r328170 "[DAG] Enforce stricter NodeId invariant during Instruction selection" Reverting patch as NodeId invariant change is causing pathological increases in compile time on PPC llvm-svn: 327197
* [DAG] Enforce stricter NodeId invariant during Instruction selectionNirav Dave2018-03-091-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instruction Selection makes use of the topological ordering of nodes by node id (a node's operands have smaller node id than it) when doing cycle detection. During selection we may violate this property as a selection of multiple nodes may induce a use dependence (and thus a node id restriction) between two unrelated nodes. If a selected node has an unselected successor this may allow us to miss a cycle in detection an invalid selection. This patch fixes this by marking all unselected successors of a selected node have negated node id. We avoid pruning on such negative ids but still can reconstruct the original id for pruning. In-tree targets have been updated to replace DAG-level replacements with ISel-level ones which enforce this property. This preemptively fixes PR36312 before triggering commit r324359 relands Reviewers: craig.topper, bogner, jyknight Subscribers: arsenm, nhaehnle, javed.absar, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D43198 llvm-svn: 327170
* [SystemZ] NFC refactoring in SystemZHazardRecognizer.Jonas Paulsson2018-03-071-5/+2
| | | | | | | Use Reset() after emitting a call. Review: Ulrich Weigand llvm-svn: 326881
* [SystemZ] Improve getCurrCycleIdx() in SystemZHazardRecognizer.Jonas Paulsson2018-03-072-9/+20
| | | | | | | | | | | getCurrCycleIdx() returns the decoder cycle index which the next candidate SU will be placed on. This patch improves this method by passing the candidate SU to it so that if SU will begin a new group, the index of that group is returned instead. Review: Ulrich Weigand llvm-svn: 326880
* [SystemZ] NFC refactoring in SystemZHazardRecognizer.Jonas Paulsson2018-03-071-4/+8
| | | | | | | | Handle the not-taken branch in emitInstruction() where the TakenBranch argument is available. This is cleaner than relying on EmitInstruction(). Review: Ulrich Weigand llvm-svn: 326879
* [SystemZ] Improved debug dumping during post-RA scheduling.Jonas Paulsson2018-03-074-70/+102
| | | | | Review: Ulrich Weigand llvm-svn: 326878
* [SystemZ] Allow LRV/STRV with volatile memory accessesUlrich Weigand2018-03-021-6/+1
| | | | | | | | The byte-swapping loads and stores do not actually perform multiple accesses to their memory operand, so they are OK to use with volatile memory operands as well. Remove overly cautious check. llvm-svn: 326613
* [SystemZ] Add support for anyregcc calling conventionUlrich Weigand2018-03-023-12/+44
| | | | | | | | | | | | | This adds back-end support for the anyregcc calling convention for use with patchpoints. Since all registers are considered call-saved with anyregcc (except for 0 and 1 which may still be clobbered by PLT stubs and the like), this required adding support for saving and restoring vector registers in prologue/epilogue code for the first time. This is not used by any other calling convention. llvm-svn: 326612
* [SystemZ] Support stackmaps and patchpointsUlrich Weigand2018-03-024-1/+157
| | | | | | | This adds back-end support for the @llvm.experimental.stackmap and @llvm.experimental.patchpoint intrinsics. llvm-svn: 326611
* [SystemZ] Fix common-code users of stack sizeUlrich Weigand2018-03-022-47/+11
| | | | | | | | | | | | | | | | | | | On SystemZ we need to provide a register save area of 160 bytes to any called function. This size needs to be added when allocating stack in the function prologue. However, it was not accounted for as part of MachineFrameInfo::getStackSize(); instead the back-end used a private routine getAllocatedStackSize(). This is OK for code-gen purposes, but it breaks other users of the getStackSize() routine, in particular it breaks the recently- added -stack-size-section feature. Fix this by updating the main stack size tracked by common code (in emitPrologue) instead of using the private routine. No change in code generation intended. llvm-svn: 326610
* [SystemZ] Support vector registers in inline asmUlrich Weigand2018-03-022-9/+36
| | | | | | | | This adds support for specifying vector registers for use with inline asm statements, either via the 'v' constraint or by explicit register names (v0 ... v31). llvm-svn: 326609
* [TLS] use emulated TLS if the target supports only this modeChih-Hung Hsieh2018-02-281-1/+1
| | | | | | | | | | | | | | | Emulated TLS is enabled by llc flag -emulated-tls, which is passed by clang driver. When llc is called explicitly or from other drivers like LTO, missing -emulated-tls flag would generate wrong TLS code for targets that supports only this mode. Now use useEmulatedTLS() instead of Options.EmulatedTLS to decide whether emulated TLS code should be generated. Unit tests are modified to run with and without the -emulated-tls flag. Differential Revision: https://reviews.llvm.org/D42999 llvm-svn: 326341
* [SystemZ] Make sure SelectCode() is not called on a target opcode.Jonas Paulsson2018-02-271-1/+2
| | | | | | | | | Since getNode() might not always return the requsted opcode, for instance if called with (ISD::AND, -1) arguments, there should be a check so that SelectCode() is only called when appropriate. Review: Ulrich Weigand llvm-svn: 326178
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
* [SystemZ] Check the bitwidth before calling isInt/isUInt.Jonas Paulsson2018-01-311-1/+2
| | | | | | | | | Since these methods will assert if the integer does not fit into 64 bits, it is necessary to do this check before calling them in supportedAddressingMode(). Review: Ulrich Weigand. llvm-svn: 323866
* [SelectionDAGISel] Add a debug print before call to Select. Adjust where ↵Craig Topper2018-01-261-3/+0
| | | | | | | | | | | | blank lines are printed during isel process to make things more sensibly grouped. Previously some targets printed their own message at the start of Select to indicate what they were selecting. For the targets that didn't, it means there was no print of the root node before any custom handling in the target executed. So if the target did something custom and never called SelectNodeCommon, no print would be made. For the targets that did print a message in Select, if they didn't custom handle a node SelectNodeCommon would reprint the root node before walking the isel table. It seems better to just print the message before the call to Select so all targets behave the same. And then remove the root node printing from SelectNodeCommon and just leave a message that says we're starting the table search. There were also some oddities in blank line behavior. Usually due to a \n after a call to SelectionDAGNode::dump which already inserted a new line. llvm-svn: 323551
* [SystemZ] Fix bootstrap failure due to invalid DAG loopUlrich Weigand2018-01-221-2/+21
| | | | | | | | | | | | | | The change in r322988 caused a failure in the bootstrap build bot. The problem was that directly gluing a BR_CCMASK node to a compare-and-swap could lead to issues if other nodes were chained in between. There is then no way to create a topological sort that respects both the chain sequence and the glue property. Fixed for now by rejecting the optimization in this case. As a future enhancement, we may be able to handle additional cases by swapping chain links around. llvm-svn: 323129
* [SystemZ] Prefer LOCHI over generating IPM sequencesUlrich Weigand2018-01-191-0/+5
| | | | | | | | On current machines we have load-on-condition instructions that can be used to directly implement the SETCC semantics. If we have those, it is always preferable to use them instead of generating the IPM sequence. llvm-svn: 322989
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