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| author | Craig Topper <craig.topper@intel.com> | 2018-03-18 19:56:15 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-18 19:56:15 +0000 |
| commit | e1d6a4df1cb48da825346a407134cd14120a1b45 (patch) | |
| tree | f3702ea82c7f828a9714495782b79fde5b75739a /llvm/lib/Target/SystemZ | |
| parent | 203876f104c6f45262c70ddf4c9b77ea2b9523c7 (diff) | |
| download | bcm5719-llvm-e1d6a4df1cb48da825346a407134cd14120a1b45.tar.gz bcm5719-llvm-e1d6a4df1cb48da825346a407134cd14120a1b45.zip | |
[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
This is similar to the check later when we remap some of the instructions from one class to a new one. But if we reuse the class we don't get to do that check.
So many CPUs have violations of this check that I had to add a flag to the SchedMachineModel to allow it to be disabled. Hopefully we can get those cleaned up quickly and remove this flag.
A lot of the violations are due to overlapping regular expressions, but that's not the only kind of issue it found.
llvm-svn: 327808
Diffstat (limited to 'llvm/lib/Target/SystemZ')
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZScheduleZ13.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZScheduleZ14.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZScheduleZ196.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td | 3 |
4 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td index 72543c1eaee..ab835f634e6 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td @@ -24,6 +24,9 @@ def Z13Model : SchedMachineModel { // Extra cycles for a mispredicted branch. let MispredictPenalty = 20; + + // FIXME: Remove when all errors have been fixed. + let FullInstRWOverlapCheck = 0; } let SchedModel = Z13Model in { diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td index 698eb5627d1..e60e5583b50 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td @@ -24,6 +24,9 @@ def Z14Model : SchedMachineModel { // Extra cycles for a mispredicted branch. let MispredictPenalty = 20; + + // FIXME: Remove when all errors have been fixed. + let FullInstRWOverlapCheck = 0; } let SchedModel = Z14Model in { diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td index 4d986e8391c..43d18aa54a5 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td @@ -24,6 +24,9 @@ def Z196Model : SchedMachineModel { // Extra cycles for a mispredicted branch. let MispredictPenalty = 16; + + // FIXME: Remove when all errors have been fixed. + let FullInstRWOverlapCheck = 0; } let SchedModel = Z196Model in { diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td index a0f2115eb9d..c7f9a6e7cb6 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td @@ -24,6 +24,9 @@ def ZEC12Model : SchedMachineModel { // Extra cycles for a mispredicted branch. let MispredictPenalty = 16; + + // FIXME: Remove when all errors have been fixed. + let FullInstRWOverlapCheck = 0; } let SchedModel = ZEC12Model in { |
