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* Add file comment. Include <vector> and <string>. Update include guardsBrian Gaeke2003-06-041-5/+32
| | | | | | | to reflect file's current location. Add definition of class MappingInfo. llvm-svn: 6616
* Revert brians patch to get mapping info working againChris Lattner2003-06-041-9/+4
| | | | | | sorry dude llvm-svn: 6615
* Had to comment out a line in outByte() to get it to compile because Out and ↵Tanya Lattner2003-06-041-1/+1
| | | | | | | | tmp were undeclared. I was not sure what Brian wanted, so I will let him fix this. But now it compiles. llvm-svn: 6614
* * Instead of re-inventing the MachineConstantPool emitter that's already givenMisha Brukman2003-06-042-111/+146
| | | | | | | | | | | | | | | | | | | | in Emitter.cpp, just convert the Sparc version of the constant pool into what's already supported and inter-operate. * Implemented a first pass at lazy function resolution in the JITResolver. That required adding a SparcV9CodeEmitter pointer to simplify generating bit-patterns of the instructions. * SparcV9CodeEmitter now creates and destroys static TheJITResolver, which makes sense because the SparcV9CodeEmitter is the only user of TheJITResolver, and lives for the entire duration of the JIT (via PassManager which lives in VM). * Changed all return values in the JITResolver to uint64_t because of the 64-bit Sparc architecture. * Added a new version of getting the value of a GlobalValue in the SparcV9CodeEmitter, which now works for already-generated functions (JITted or library functions). * Removed little-used and unused functions, cleaning up the internal view of the SparcV9CodeEmitter. llvm-svn: 6612
* Make writeNumber() void. Get ready to decouple it from .byte directive output.Brian Gaeke2003-06-041-4/+9
| | | | llvm-svn: 6609
* Added the 4.7 instruction class and all the FMOVcc instructions in them.Misha Brukman2003-06-042-37/+130
| | | | llvm-svn: 6601
* Comment out opcodes currently unused in the Sparc backend.Misha Brukman2003-06-041-0/+3
| | | | llvm-svn: 6597
* Added instruction format class 3.15 and floating-point compare instructions.Misha Brukman2003-06-042-11/+22
| | | | llvm-svn: 6594
* Avoid generating a getelementptr instruction of a functionChris Lattner2003-06-041-1/+1
| | | | llvm-svn: 6591
* Make the write*map methods more self-contained. Document some more.Brian Gaeke2003-06-031-42/+57
| | | | llvm-svn: 6589
* I documented this file, in an attempt to understand it, with a view towardBrian Gaeke2003-06-031-56/+73
| | | | | | | | | | | rewriting it. I also vacuumed out all the commented-out code and inaccurate comments, etc. (We need to put the mapping information in a data structure so that we can pass it out to the JIT, instead of automagically converting it to .byte directives.) llvm-svn: 6574
* Use the new -o tablegen optionChris Lattner2003-06-031-4/+1
| | | | llvm-svn: 6572
* Constants are laid out in memory in PC-relative form.Misha Brukman2003-06-031-1/+1
| | | | llvm-svn: 6568
* Added opcode conversion for conditional move of integers.Misha Brukman2003-06-031-0/+50
| | | | llvm-svn: 6567
* * Convert load/store opcodes from register to immediate forms.Misha Brukman2003-06-031-9/+11
| | | | | | * Stop code from wrapping to the next line. llvm-svn: 6566
* Convert load/store opcodes from register to immediate forms, if necessary.Misha Brukman2003-06-031-4/+13
| | | | llvm-svn: 6565
* Store instructions are different from other Format 3.1/3.2 instructions in thatMisha Brukman2003-06-032-7/+43
| | | | | | | they prefer the destination register to be last. Thus, two new classes were made for them that accomodate for having this layout of operands (F3_1rd, F3_2rd). llvm-svn: 6564
* * Added section A.34: Move FP register on int reg condition (FMOVr)Misha Brukman2003-06-031-13/+42
| | | | | | | * Labeled sections that are not currently used in the Sparc backend as not requiring completion at this time. llvm-svn: 6562
* * Removed unused classes (rd field is always mentioned last); fixed comments.Misha Brukman2003-06-031-38/+34
| | | | | | | * Added instruction classes which start building from rs1, then rs2, and rd. * Fixed order of operands in classes 4.1 and 4.2; added 4.6 . llvm-svn: 6561
* * Removed unused classes: the rd field is always mentioned as the last reg.Misha Brukman2003-06-031-57/+19
| | | | | | | | | * Added new classes which start building from rs1, adding rs2, and then rd. * Fixed order of operands in classes 3.11, 3.12, 3.16, and 3.17 . * Fixed comments to reflect Real Life (tm). * Removed "don't care" commented out assignments and dead classes (#if 0). llvm-svn: 6560
* The rd field goes after the immediate field in format 2.1 instructions.Misha Brukman2003-06-031-2/+1
| | | | llvm-svn: 6559
* Added MOVR (move int reg on register condition), aka comparison with zero.Misha Brukman2003-06-023-8/+48
| | | | | | | None of these instructions are actually used in the Sparc backend, so no changes were required in the instruction selector. llvm-svn: 6549
* SparcInstr.def: added 'r' and 'i' versions of MOV(F)cc instructionsMisha Brukman2003-06-024-85/+193
| | | | | | | | | | | | | | | SparcInstrSelection.cpp: * Fixed opcodes to return correct 'i' version since the two functions are each only used in one place. * Changed name of function to have an 'i' in the name to signify that they each return an immediate form of the opcode. * Added a warning if either of the functions is ever used in a context which requires a register-version opcode. SparcV9_F4.td: fixed class F4_3, added F4_4 and notes that F4_{1,2} need fixing SparcV9.td: added the MOV(F)cc instructions llvm-svn: 6548
* * Added casts to/from floating-point to integers.Misha Brukman2003-06-021-90/+187
| | | | | | * Changed // comments to #ifdef 0 to maintain syntax highlighting. llvm-svn: 6546
* Clean up after merging in SparcEmitter.cpp; branches and return work again.Misha Brukman2003-06-021-11/+40
| | | | llvm-svn: 6536
* Merged in tools/lli/JIT/SparcEmitter.cpp, coupled with the JITResolver takenMisha Brukman2003-06-022-19/+275
| | | | | | from lib/Target/X86/X86CodeEmitter.cpp . llvm-svn: 6530
* Deal with %lo/%lm/%hm/%hh flags in getMachineOpValue().Brian Gaeke2003-06-021-10/+21
| | | | llvm-svn: 6522
* Make the .inc file depend on $(TBLGEN), so that changes to TableGen followedBrian Gaeke2003-06-011-1/+1
| | | | | | by a re-link of TableGen will notify Make to rebuild the .inc file. llvm-svn: 6512
* Add map info for arguments to call (copies)Anand Shukla2003-06-011-1/+11
| | | | llvm-svn: 6503
* Several bug fixes: globals in call operands were not being pulled out;Vikram S. Adve2003-05-311-12/+43
| | | | | | | | globals in some other places may not have been pulled out either; globals in phi operands were being put just before the phi instead of in the predecessor basic blocks. llvm-svn: 6466
* Extensive changes to the way code generation occurs for functionVikram S. Adve2003-05-314-433/+554
| | | | | | | | | | | | | | call arguments and return values: Now all copy operations before and after a call are generated during selection instead of during register allocation. The values are copied to virtual registers (or to the stack), but in the former case these operands are marked with the correct physical registers according to the calling convention. Although this complicates scheduling and does not work well with live range analysis, it simplifies the machine-dependent part of register allocation. llvm-svn: 6465
* Reverting previous beautification changes.Vikram S. Adve2003-05-312-384/+408
| | | | llvm-svn: 6464
* Removed useless code -- the byte order of output code is correct as is.Misha Brukman2003-05-311-6/+1
| | | | llvm-svn: 6462
* The 'rd' register is consistently mentioned last in instruction definitions.Misha Brukman2003-05-311-4/+16
| | | | | | Created new classes from which instructions inherit their ordering of fields. llvm-svn: 6461
* * Put back into action SLL/SRL/SRA{r,i}6 instructionsMisha Brukman2003-05-311-8/+8
| | | | | | * Fixed page numbers referring to the Sparc manual llvm-svn: 6460
* Code beautification, no functional changes.Misha Brukman2003-05-312-408/+384
| | | | llvm-svn: 6459
* Enabling some of these passes causes lli to breakMisha Brukman2003-05-311-0/+6
| | | | llvm-svn: 6457
* The actual order of parameters in a 2-reg-immediate assembly instructions isMisha Brukman2003-05-311-2/+34
| | | | | | "rs1, imm, rd": most importantly, rd goes last. llvm-svn: 6456
* Added:Misha Brukman2003-05-302-15/+108
| | | | | | | * ability to save BasicBlock references to be resolved later * register remappings from the enum values to the real hardware numbers llvm-svn: 6449
* Fixed the namespace to match SparcInternals.h; added notes on some missingMisha Brukman2003-05-301-5/+18
| | | | | | sections of instructions. llvm-svn: 6448
* The register types need to be visible outside of the class to be useful.Misha Brukman2003-05-301-14/+13
| | | | | | For one, converting register numbers based on class in the code emitter. llvm-svn: 6447
* Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes.Misha Brukman2003-05-302-448/+457
| | | | | | | Code beautification for the rest of the code: changed layout to match the rest of the code base. llvm-svn: 6446
* Make LLI behave just like LLC with regard to the compile passes it uses.Misha Brukman2003-05-301-0/+15
| | | | llvm-svn: 6444
* Made the register and immediate versions of instructions consecutive.Misha Brukman2003-05-301-7/+5
| | | | llvm-svn: 6439
* Because the format of the shift instructions is `shift r, shcnt, r', theMisha Brukman2003-05-301-7/+11
| | | | | | | | | | | | | instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that implies that the two registers are the first two parameters to the instruction. Thus I made the instructions inherit from F3rd again, and manually added an rs1 field AFTER the shcnt field in the instruction, which maps to the appropriate place in the instruction. The other changes are just elimination of unnecessary spaces. llvm-svn: 6437
* Makefile: Make SparcV9CodeEmitter.inc depend on SparcV9_F*.td as well.Brian Gaeke2003-05-302-3/+7
| | | | | | | SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also, their fields were totally screwed up. This seems to fix the problem. llvm-svn: 6429
* Since there is now another derived .inc file, ignore them all.Misha Brukman2003-05-291-1/+1
| | | | llvm-svn: 6411
* Use an absolute path to TableGen because not everyone (e.g. automatic tester)Misha Brukman2003-05-291-1/+1
| | | | | | has their path set up by this point. llvm-svn: 6410
* When TableGen finds an error in the SparcV9.td file, it exits with a non-zeroMisha Brukman2003-05-291-1/+4
| | | | | | | | | | | exit code. This, in turn, makes an empty file SparcV9CodeEmitter.inc, and only much later, produces a link error because the key function that TableGen creates isn't found. Using a temporary file in the middle forces a good .INC file to be generated by TableGen, and it will keep trying until you fix the input file. llvm-svn: 6392
* Fixed to use the correct format of the instruction.Misha Brukman2003-05-291-3/+3
| | | | llvm-svn: 6390
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