diff options
| author | Brian Gaeke <gaeke@uiuc.edu> | 2003-05-30 08:02:14 +0000 |
|---|---|---|
| committer | Brian Gaeke <gaeke@uiuc.edu> | 2003-05-30 08:02:14 +0000 |
| commit | d380f293777c58ee3e1e825e59ffd648628f903a (patch) | |
| tree | 40c11b7534fbefd183b52dafe7eadf588a9cb86d /llvm/lib/Target/Sparc | |
| parent | 38d88c07f418ec227d98f715f27ea8706c1027fc (diff) | |
| download | bcm5719-llvm-d380f293777c58ee3e1e825e59ffd648628f903a.tar.gz bcm5719-llvm-d380f293777c58ee3e1e825e59ffd648628f903a.zip | |
Makefile: Make SparcV9CodeEmitter.inc depend on SparcV9_F*.td as well.
SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also,
their fields were totally screwed up. This seems to fix the problem.
llvm-svn: 6429
Diffstat (limited to 'llvm/lib/Target/Sparc')
| -rw-r--r-- | llvm/lib/Target/Sparc/Makefile | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcV9_F3.td | 8 |
2 files changed, 7 insertions, 3 deletions
diff --git a/llvm/lib/Target/Sparc/Makefile b/llvm/lib/Target/Sparc/Makefile index a18719354ef..8ac4d5b498e 100644 --- a/llvm/lib/Target/Sparc/Makefile +++ b/llvm/lib/Target/Sparc/Makefile @@ -36,7 +36,7 @@ SparcV9CodeEmitter.cpp: SparcV9CodeEmitter.inc TEMP_EMITTER_INC = _temp_emitter.inc -SparcV9CodeEmitter.inc: SparcV9.td +SparcV9CodeEmitter.inc: SparcV9.td SparcV9_F2.td SparcV9_F3.td SparcV9_F4.td SparcV9_Reg.td @echo "TableGen-erating $@" cpp -P SparcV9.td | $(TBLGEN) -gen-emitter > $(TEMP_EMITTER_INC) mv -f $(TEMP_EMITTER_INC) SparcV9CodeEmitter.inc diff --git a/llvm/lib/Target/Sparc/SparcV9_F3.td b/llvm/lib/Target/Sparc/SparcV9_F3.td index cabbde18399..294d1d7c6d0 100644 --- a/llvm/lib/Target/Sparc/SparcV9_F3.td +++ b/llvm/lib/Target/Sparc/SparcV9_F3.td @@ -108,9 +108,11 @@ class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1rs2 { //set Inst{11-5} = dontcare; } -class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3 { +class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1 { bits<5> shcnt; + set op = opVal; + set op3 = op3Val; set Name = name; set Inst{13} = 1; // i field = 1 set Inst{12} = 0; // x field = 0 @@ -118,9 +120,11 @@ class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3 { set Inst{4-0} = shcnt; } -class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3 { +class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1 { bits<6> shcnt; + set op = opVal; + set op3 = op3Val; set Name = name; set Inst{13} = 1; // i field = 1 set Inst{12} = 1; // x field = 1 |
