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| author | Misha Brukman <brukman+llvm@gmail.com> | 2003-06-03 03:20:57 +0000 | 
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2003-06-03 03:20:57 +0000 | 
| commit | 3cdf52a644953e21e7e002619123ca6e160bb121 (patch) | |
| tree | 69977f7767e83582d551deee7597f9023b7039dc /llvm/lib/Target/Sparc | |
| parent | b54bf54065806240e23cc0e1ea21c6794eac044f (diff) | |
| download | bcm5719-llvm-3cdf52a644953e21e7e002619123ca6e160bb121.tar.gz bcm5719-llvm-3cdf52a644953e21e7e002619123ca6e160bb121.zip | |
Convert load/store opcodes from register to immediate forms, if necessary.
llvm-svn: 6565
Diffstat (limited to 'llvm/lib/Target/Sparc')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcInstrInfo.cpp | 17 | 
1 files changed, 13 insertions, 4 deletions
| diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index 55f7ece1f5d..57ce3cd36a7 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -478,6 +478,7 @@ UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,      // Generate the load instruction      int64_t zeroOffset = 0;           // to avoid ambiguity with (Value*) 0      unsigned Opcode = ChooseLoadInstruction(val->getType()); +    Opcode = convertOpcodeFromRegToImm(Opcode);      mvec.push_back(BuildMI(Opcode, 3).addReg(addrReg).                     addSImm(zeroOffset).addRegDef(dest)); @@ -532,7 +533,9 @@ UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,    }    unsigned FPReg = target.getRegInfo().getFramePointer(); -  mvec.push_back(BuildMI(ChooseStoreInstruction(storeType), 3) +  unsigned StoreOpcode = ChooseStoreInstruction(storeType); +  StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode); +  mvec.push_back(BuildMI(StoreOpcode, 3)                   .addReg(storeVal).addMReg(FPReg).addSImm(offset));    // Load instruction loads [%fp+offset] to `dest'. @@ -541,7 +544,9 @@ UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,    // On SparcV9: float for int or smaller, double for long.    //     const Type* loadType = (srcSize <= 4)? Type::FloatTy : Type::DoubleTy; -  mvec.push_back(BuildMI(ChooseLoadInstruction(loadType), 3) +  unsigned LoadOpcode = ChooseLoadInstruction(loadType); +  LoadOpcode = convertOpcodeFromRegToImm(LoadOpcode); +  mvec.push_back(BuildMI(LoadOpcode, 3)                   .addMReg(FPReg).addSImm(offset).addRegDef(dest));  } @@ -577,7 +582,9 @@ UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,    // Store instruction stores `val' to [%fp+offset].    // The store opCode is based only the source value being copied.    //  -  mvec.push_back(BuildMI(ChooseStoreInstruction(opTy), 3) +  unsigned StoreOpcode = ChooseStoreInstruction(opTy); +  StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);   +  mvec.push_back(BuildMI(StoreOpcode, 3)                   .addReg(val).addMReg(FPReg).addSImm(offset));    // Load instruction loads [%fp+offset] to `dest'. @@ -588,7 +595,9 @@ UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,    // ensure correct sign-extension for UByte, UShort or UInt:    //     const Type* loadTy = (opTy == Type::FloatTy)? Type::IntTy : Type::LongTy; -  mvec.push_back(BuildMI(ChooseLoadInstruction(loadTy), 3).addMReg(FPReg) +  unsigned LoadOpcode = ChooseLoadInstruction(loadTy); +  LoadOpcode = convertOpcodeFromRegToImm(LoadOpcode); +  mvec.push_back(BuildMI(LoadOpcode, 3).addMReg(FPReg)                   .addSImm(offset).addRegDef(dest));  } | 

