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* [RISCV] Lower inline asm constraint A for RISC-VLewis Revill2019-08-163-0/+23
* [llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere2019-08-153-6/+6
* [risc-v] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-126-49/+49
* [RISCV] Fix ICE in isDesirableToCommuteWithShiftSam Elliott2019-08-121-2/+4
* [RISCV] Allow ABI Names in Inline Assembly ConstraintsSam Elliott2019-08-081-34/+78
* [RISCV] Minimal stack realignment supportSam Elliott2019-08-081-2/+46
* [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensionsShiva Chen2019-08-061-0/+24
* [LLVM][Alignment] Introduce Alignment TypeGuillaume Chatelet2019-08-051-1/+1
* Emit diagnostic if an inline asm constraint requires an immediateBill Wendling2019-08-031-0/+4
* [RISCV] Add Custom Parser for Atomic Memory OperandsSam Elliott2019-08-014-4/+113
* [RISCV] Support 'f' Inline Assembly ConstraintSam Elliott2019-07-312-0/+22
* [RISCV] Add support for lowering floating point inlineasm clobbersSimon Cook2019-07-311-0/+46
* [RISCV] Fix uninitialized variable after call to evaluateConstantImmFrancis Visoiu Mistrih2019-07-291-22/+22
* [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.Hsiangkai Wang2019-07-192-0/+5
* Revert "[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame."Hsiangkai Wang2019-07-182-5/+0
* [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.Hsiangkai Wang2019-07-182-0/+5
* [RISCV] Reset NoPHIS MachineFunctionProperty in emitSelectPseudoAlex Bradbury2019-07-181-0/+1
* [RISCV] Avoid signed integer overflow UB in RISCVMatInt::generateInstSeqAlex Bradbury2019-07-181-1/+1
* [RISCV] Don't acccess an invalidated iterator in RISCVInstrInfo::removeBranchAlex Bradbury2019-07-181-2/+2
* [RISCV] Match GNU tools canonical JALR and add aliasesAlex Bradbury2019-07-161-7/+18
* [RISCV] Avoid overflow when determining number of nops for code alignAlex Bradbury2019-07-161-2/+6
* [RISCV] Fix a potential issue in shouldInsertFixupForCodeAlign()Alex Bradbury2019-07-161-4/+3
* [RISCV][NFC] Split PseudoCALL pattern out from instructionAlex Bradbury2019-07-161-2/+2
* [RISCV][NFC] Fix HasStedExtA -> HasStdExtA typo in commentAlex Bradbury2019-07-161-1/+1
* [RISCV] Make RISCVELFObjectWriter::getRelocType check IsPCRelAlex Bradbury2019-07-161-25/+36
* [RISCV] Allow parsing dot '.' in assemblySam Elliott2019-07-121-0/+1
* [RISCV] Fix ICE in isDesirableToCommuteWithShiftSam Elliott2019-07-091-1/+1
* [RISCV] Fix RISCVTTIImpl::getIntImmCost for immediates where getMinSignedBits...Alex Bradbury2019-07-091-1/+3
* [RISCV] Specify registers used in DWARF exception handlingAlex Bradbury2019-07-082-0/+20
* [RISCV] Support z and i operand modifiersAlex Bradbury2019-07-081-9/+27
* [RISCV] Support @llvm.readcyclecounter() IntrinsicSam Elliott2019-07-054-1/+107
* [RISCV][NFC] Replace hard-coded CSR duplication with symbolic referencesSam Elliott2019-07-054-39/+36
* [RISCV] Delete a ctor that is commented out. NFCFangrui Song2019-07-051-2/+0
* [RISCV] Add break; to the last switch caseFangrui Song2019-07-011-0/+1
* [RISCV] Add pseudo instruction for calls with explicit registerLewis Revill2019-06-264-11/+38
* CodeGen: Introduce a class for registersMatt Arsenault2019-06-242-2/+2
* [RISCV] Add RISCV-specific TargetTransformInfoSam Elliott2019-06-216-2/+154
* [RISCV] Allow parsing immediates that use tilde & exclaimLewis Revill2019-06-191-0/+4
* [RISCV] Fix failure to parse parenthesized immediatesLewis Revill2019-06-191-3/+8
* [RISCV] Add lowering of global TLS addressesLewis Revill2019-06-196-0/+169
* [RISCV] Prevent re-ordering some adds after shiftsSam Elliott2019-06-184-4/+75
* [RISCV] Lower calls through PLTLewis Revill2019-06-183-4/+18
* [DAGCombiner] [CodeGenPrepare] More comprehensive GEP splittingLuis Marques2019-06-171-0/+1
* [RISCV] Simplify RISCVAsmBackend::writeNopData(). NFCFangrui Song2019-06-151-7/+3
* [RISCV] Add CFI directives for RISCV prologue/epilog.Hsiangkai Wang2019-06-123-4/+78
* [RISCV] Add lowering of addressing sequences for PICLewis Revill2019-06-116-16/+64
* [RISCV] Lower inline asm constraints I, J & K for RISC-VLewis Revill2019-06-112-0/+42
* Revert CMake: Make most target symbols hidden by defaultTom Stellard2019-06-116-6/+6
* CMake: Make most target symbols hidden by defaultTom Stellard2019-06-106-6/+6
* [RISCV] Support Bit-Preserving FP in F/D ExtensionsSam Elliott2019-06-072-0/+7
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