summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/RISCV
Commit message (Expand)AuthorAgeFilesLines
* [RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlen...Alex Bradbury2017-12-152-9/+33
* [RISCV] Enable emission of alias instructions by defaultAlex Bradbury2017-12-151-3/+1
* [RISCV] Define sfence.vma InstAliases to match the GNU RISC-V toolsAlex Bradbury2017-12-131-0/+3
* [RISCV] Implement floating point assembler pseudo instructionsAlex Bradbury2017-12-132-0/+46
* [RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming conv...Alex Bradbury2017-12-132-98/+100
* [RISCV][NFC] Put isSImm6 and simm6 td definition in correct sorted positionAlex Bradbury2017-12-132-22/+22
* [RISCV] MC layer support for the remaining RVC instructionsAlex Bradbury2017-12-135-20/+390
* [RISCV][NFC] Formatting fix in RISCVInstrInfo.tdAlex Bradbury2017-12-121-4/+4
* [RISCV] Implement assembler pseudo instructions for RV32I and RV64IAlex Bradbury2017-12-123-1/+96
* [RISCV] MC layer support for the instructions added in the privileged specAlex Bradbury2017-12-121-0/+42
* [RISCV] Add custom CC_RISCV calling convention and improved call supportAlex Bradbury2017-12-114-48/+373
* [RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestoreAlex Bradbury2017-12-111-0/+5
* [RISCV] Implement prolog and epilog insertionAlex Bradbury2017-12-112-3/+159
* [RISCV] Support lowering FrameIndexAlex Bradbury2017-12-115-8/+85
* [RISCV] MC layer support for the jump/branch instructions of the RVC extensionAlex Bradbury2017-12-077-2/+164
* [RISCV] MC layer support for load/store instructions of the C (compressed) ex...Alex Bradbury2017-12-0711-22/+406
* [RISCV][NFC] Use TargetRegisterClass::hasSubClassEq in storeRegToStackSlot/lo...Alex Bradbury2017-12-071-2/+2
* [RISCV] MC layer support for the standard RV64D instruction set extensionAlex Bradbury2017-12-071-0/+30
* [RISCV] MC layer support for the standard RV64F instruction set extensionAlex Bradbury2017-12-071-0/+22
* [RISCV] MC layer support for the standard RV64A instruction set extensionAlex Bradbury2017-12-071-0/+14
* [RISCV] MC layer support for the standard RV64M instruction set extensionAlex Bradbury2017-12-071-0/+8
* [RISCV] MC layer support for the standard RV64I instructionsAlex Bradbury2017-12-074-18/+111
* [RISCV] MC layer support for the standard RV32D instruction set extensionAlex Bradbury2017-12-077-0/+258
* [RISCV] MC layer support for the standard RV32F instruction set extensionAlex Bradbury2017-12-0711-13/+397
* [RISCV][NFC] Remove unnecessary {} around single statement if blockAlex Bradbury2017-11-211-2/+1
* [RISCV][NFC] Clean up RISCVDAGToDAGISel::SelectAlex Bradbury2017-11-211-14/+9
* [RISCV] Use register X0 (ZERO) for constant 0Alex Bradbury2017-11-211-0/+30
* [RISCV] Support and tests for a variety of additional LLVM IR constructsAlex Bradbury2017-11-214-15/+121
* [RISCV] Implement lowering of ISD::SELECTAlex Bradbury2017-11-213-1/+174
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-173-3/+3
* [RISCV] Fix 64-bit data layout mismatch between backend and target descriptionMandeep Singh Grang2017-11-161-1/+1
* Fix RISCV build after r318352Azharuddin Mohammed2017-11-161-2/+2
* [RISCV] Silence an unused variable warning in release builds [NFC]Mandeep Singh Grang2017-11-102-5/+5
* [RISCV] MC layer support for the standard RV32A instruction set extensionAlex Bradbury2017-11-096-12/+128
* [RISCV] MC layer support for the standard RV32M instruction set extensionAlex Bradbury2017-11-094-4/+45
* [RISCV] Initial support for function callsAlex Bradbury2017-11-088-4/+186
* [RISCV] Codegen for conditional branchesAlex Bradbury2017-11-088-4/+118
* [RISCV] Codegen support for memory operations on global addressesAlex Bradbury2017-11-085-22/+99
* [RISCV] Codegen support for memory operationsAlex Bradbury2017-11-084-0/+47
* [RISCV] Codegen support for materializing constantsAlex Bradbury2017-11-081-0/+24
* [NFCI] Ensure TargetOpcode::* are compatible with guessInstructionProperties=0Alex Bradbury2017-11-081-3/+1
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-082-3/+3
* Move TargetFrameLowering.h to CodeGen where it's implementedDavid Blaikie2017-11-032-2/+2
* [RISCV] Add missing hunk from r316188Alex Bradbury2017-10-191-1/+3
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-1922-11/+938
* [RISCV] RISCVAsmParser: early exit if RISCVOperand isn't immediate as expectedAlex Bradbury2017-10-191-0/+10
* [RISCV][NFC] Drop unused parameter from createImm helper in RISCVAsmParserAlex Bradbury2017-10-191-4/+3
* [RISCV] Prepare for the use of variable-sized register classesAlex Bradbury2017-10-198-220/+276
* [RISCV] Bugfix createRISCVELFObjectWriterAlex Bradbury2017-10-181-1/+1
* Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine"Matthias Braun2017-10-122-4/+4
OpenPOWER on IntegriCloud