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| author | Alex Bradbury <asb@lowrisc.org> | 2017-10-19 21:43:29 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-10-19 21:43:29 +0000 |
| commit | c6c4e8bd5aa536ee5513539a5d42e9743291f1dd (patch) | |
| tree | 2748cf1c23d84fd62bb647f53dc3444259e5d8da /llvm/lib/Target/RISCV | |
| parent | 8971842f43b978e72aa40cf0a94c3d39c7a74c85 (diff) | |
| download | bcm5719-llvm-c6c4e8bd5aa536ee5513539a5d42e9743291f1dd.tar.gz bcm5719-llvm-c6c4e8bd5aa536ee5513539a5d42e9743291f1dd.zip | |
[RISCV] Add missing hunk from r316188
r316188 didn't set guessInstructionProperties=1 as it should have done.
llvm-svn: 316189
Diffstat (limited to 'llvm/lib/Target/RISCV')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCV.td | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index da919acad36..54aa570e13b 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -40,7 +40,9 @@ def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; //===----------------------------------------------------------------------===// def RISCVInstrInfo : InstrInfo { - let guessInstructionProperties = 0; + // TODO: disable guessInstructionProperties when + // https://reviews.llvm.org/D37065 lands. + let guessInstructionProperties = 1; } def RISCVAsmParser : AsmParser { |
