[RISCV] MC layer support for the standard RV32M instruction set extension

llvm-svn: 317788

4 files changed, 45 insertions, 4 deletions

diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index da919acad36..d8581f8d03c 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -13,11 +13,16 @@ include "llvm/Target/Target.td"
 // RISC-V subtarget features and instruction predicates.
 //===----------------------------------------------------------------------===//
 
-def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true",
-                                    "Implements RV64">;
+def FeatureStdExtM : SubtargetFeature<"m", "HasStdExtM", "true",
+                           "'M' (Integer Multiplication and Division)">;
+def HasStdExtM     : Predicate<"Subtarget->hasStdExtM()">,
+                           AssemblerPredicate<"FeatureStdExtM">;
 
-def RV64         : HwMode<"+64bit">;
-def RV32         : HwMode<"-64bit">;
+def Feature64Bit   : SubtargetFeature<"64bit", "HasRV64", "true",
+                           "Implements RV64">;
+
+def RV64           : HwMode<"+64bit">;
+def RV32           : HwMode<"-64bit">;
 
 //===----------------------------------------------------------------------===//
 // Registers, calling conventions, instruction descriptions.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 23f218fda8f..e95a8e1c813 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -399,3 +399,9 @@ def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                               [(CallSeqEnd timm:$amt1, timm:$amt2)]>;
 } // Defs = [X2], Uses = [X2]
+
+//===----------------------------------------------------------------------===//
+// Standard extensions
+//===----------------------------------------------------------------------===//
+
+include "RISCVInstrInfoM.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td
new file mode 100644
index 00000000000..a253c1eb811
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td
@@ -0,0 +1,28 @@
+//===-- RISCVInstrInfoM.td - RISC-V 'M' instructions -------*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'M', Integer
+// Multiplication and Division instruction set extension.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtM] in {
+def MUL     : ALU_rr<0b0000001, 0b000, "mul">;
+def MULH    : ALU_rr<0b0000001, 0b001, "mulh">;
+def MULHSU  : ALU_rr<0b0000001, 0b010, "mulhsu">;
+def MULHU   : ALU_rr<0b0000001, 0b011, "mulhu">;
+def DIV     : ALU_rr<0b0000001, 0b100, "div">;
+def DIVU    : ALU_rr<0b0000001, 0b101, "divu">;
+def REM     : ALU_rr<0b0000001, 0b110, "rem">;
+def REMU    : ALU_rr<0b0000001, 0b111, "remu">;
+} // Predicates = [HasStdExtM]
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 657b0e65620..be9b04990ca 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -30,6 +30,7 @@ class StringRef;
 
 class RISCVSubtarget : public RISCVGenSubtargetInfo {
   virtual void anchor();
+  bool HasStdExtM;
   bool HasRV64 = false;
   unsigned XLen = 32;
   MVT XLenVT = MVT::i32;
@@ -66,6 +67,7 @@ public:
   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
+  bool hasStdExtM() const { return HasStdExtM; }
   bool is64Bit() const { return HasRV64; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }